System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class

• US 9,164,679 B2
• Filed: 01/05/2015
• Issued: 10/20/2015
• Est. Priority Date: 04/06/2011
• Status: Active Grant

• Current Assignee: Patents1 LLC
• Original Assignee: Patents1 LLC
• Inventors: Smith, Michael S
• Primary Examiner(s): CARDWELL, ERIC
• Application Number:
  US14/589,931
• Publication Number:
  US 20150143037A1
• Time in Patent Office: 288 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 9/44557 Code layout in executable memory
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including a first memory of a first memory class, and a second memory of a second memory class communicatively coupled to the first memory. In operation, data is fetched using a time between a plurality of threads.

Claims

1. An apparatus, comprising:

a memory sub-system capable of being communicatively coupled to a standard memory bus communicatively coupled to a processing unit, the memory sub-system including;

a first memory of a first memory class,

a second memory of a second memory class,

a first circuit communicatively coupled to the second memory, and

a second circuit communicatively coupled to the first circuit and the first memory;

wherein the apparatus is configured to, for a first thread;

receive, at the first circuit, a first command that is a special command or includes special data from the processing unit via the standard memory bus, and

in response to the first command and based on the special command or the special data, issue a second command from the first circuit to the second circuit for fetching at least a portion of first data from the first memory and transferring the at least portion of the first data from the first memory to the second memory;

wherein the apparatus is further configured to, before completion of at least one of the fetching the at least portion of the first data or the transferring the at least portion of the first data, for a second thread;

receive, at the first circuit, a third command from the processing unit via the standard memory bus that is capable of causing issuance of a fourth command from the first circuit to the second circuit for fetching at least a portion of second data from the first memory and transferring the at least portion of the second data from the first memory to the second memory;

wherein the apparatus is further configured to;

provide access to a status, and

receiving a fifth command for reading the first data.

2. The apparatus of claim 1, wherein the apparatus is configured such that the second circuit includes the first memory, and the second command includes a single command.

3. The apparatus of claim 1, wherein the apparatus is configured such that the first thread and the second thread are associated with the processing unit.

4. The apparatus of claim 1, wherein the apparatus is configured such that the first command and the third command are non-standard commands and the second command and the fourth command are standard commands.

5. The apparatus of claim 1, wherein the apparatus is configured such that the first command and the third command include read commands.

6. The apparatus of claim 1, wherein the apparatus is configured such that the first command and the third command each initiate a random access data read.

7. The apparatus of claim 1, wherein the apparatus is configured such that the third command is received before the completion of the fetching the at least portion of the first data.

8. The apparatus of claim 1, wherein the apparatus is configured such that the third command is received before the completion of the transferring the at least portion of the first data.

9. The apparatus of claim 1, wherein the apparatus is configured such that at least one of the fetching the at least portion of the second data or the transferring the at least portion of the second data associated with the second thread is completed before the completion of at least one of the fetching the at least portion of the first data or the transferring the at least portion of the first data associated with the first thread.

10. The apparatus of claim 1, wherein the apparatus is configured such that for the first thread, the fifth command is received, at the first circuit, from the processing unit via the standard memory bus, for fetching the at least portion of the first data from the second memory.

11. The apparatus of claim 10, wherein the apparatus is configured such that the fetching the at least portion of the second data associated with the second thread is completed before the fifth command associated with the first thread is received.

12. The apparatus of claim 10, wherein the apparatus is configured such that the transferring the at least portion of the second data associated with the second thread is completed before the fifth command associated with the first thread is received.

13. The apparatus of claim 10, wherein the apparatus is configured such that the fetching the at least portion of the second data associated with the second thread is completed before the at least portion of the first data is fetched from the second memory in association with the first thread.

14. The apparatus of claim 10, wherein the apparatus is configured such that the transferring the at least portion of the second data associated with the second thread is completed before the at least portion of the first data is fetched from the second memory in association with the first thread.

15. A system including the apparatus of claim 1, and further comprising the standard memory bus.

16. The apparatus of claim 1, wherein the apparatus is configured such that at least one of:

said standard memory bus includes at least one of a DDR3 bus or a DDR4 bus;

said second memory includes at least one of static random access memory, dynamic random access memory, or embedded random access memory;

said first memory or said second memory is part of the first circuit;

said first memory or said second memory is part of the second circuit;

said first command is the special command;

said first command is the special command, and the special command is received from a driver;

said first command is the special command, and the special command results from a page miss;

said first command is the special command, and the special command results from an operating system request;

said first command is the special command, and the special command is special by virtue of including the special data;

said first command is the special command, and the special command is special by virtue of the at least portion of the first data being fetched from the first memory;

said first command is the special command, and the special command includes a non-standard command;

said first command includes the special data;

said first command includes the special data, and the special data includes at least one of control data, command data, or status data;

said second command is issued based on the special command;

or

said second command is issued based on the special data.

17. An apparatus, comprising:

a memory sub-system capable of being communicatively coupled to a standard memory bus communicatively coupled to a processing unit, the memory sub-system including;

a first memory of a first memory class,

a second memory of a second memory class,

a first circuit communicatively coupled to the second memory, and

a second circuit communicatively coupled to the first circuit and the first memory;

wherein the apparatus is configured, in connection with a first thread, for;

receiving, at the first circuit, a first command that is a special command or includes special data from the processing unit via the standard memory bus,

in response to the first command and as a function of the special command or the special data, issuing a second command from the first circuit to the second circuit for fetching at least a portion of first data from the first memory and transferring the at least portion of the first data from the first memory to the second memory, and

receiving, at the first circuit, a third command from the processing unit via the standard memory bus, for fetching the at least portion of the first data from the second memory;

wherein the apparatus is further configured, in connection with a second thread, before completion of the fetching the at least portion of the first data from the second memory, for;

receiving, at the first circuit, a fourth command from the processing unit via the standard memory bus that is capable of causing issuance of a fifth command from the first circuit to the second circuit for fetching at least a portion of second data from the first memory and transferring the at least portion of the second data from the first memory to the second memory.

18. An apparatus, comprising:

a memory sub-system capable of being communicatively coupled to a standard memory bus communicatively coupled to a processing unit, the memory sub-system including;

a first memory of a first memory class,

a second memory of a second memory class,

a first circuit communicatively coupled to the second memory, and

a second circuit communicatively coupled to the first circuit and the first memory;

wherein the apparatus is configured, in connection with a first thread, for;

receiving, at the first circuit, a first command that is special from the processing unit via the standard memory bus,

in response to the first command, issuing a second command from the first circuit to the second circuit for fetching at least a portion of first data from the first memory and transferring the at least portion of the first data from the first memory to the second memory, and

receiving, at the first circuit, a third command from the processing unit via the standard memory bus, for fetching the at least portion of the first data from the second memory;

wherein the apparatus is further configured, in connection with a second thread, before receiving the third command, for;

receiving, at the first circuit, a fourth command from the processing unit via the standard memory bus that is capable of causing issuance of a fifth command from the first circuit to the second circuit for fetching at least a portion of second data from the first memory and transferring the at least portion of the second data from the first memory to the second memory.

19. The apparatus of claim 18, wherein the first memory includes flash memory, the second memory includes random access memory, and the apparatus is operable such that the first command is special by virtue of enabling DDR protocol-compliant communication of control information via the standard memory bus for controlling the second circuit to effect one or more results that are undescribed in a DDR protocol specification.

20. The apparatus of claim 18, wherein the first memory includes flash memory, the second memory includes random access memory, and the apparatus is operable such that the first command is special by virtue of including data of which a portion is used in connection with a corresponding command associated with the second circuit.