Systems and methods for enhanced data recovery in a solid state memory system

• US 9,164,828 B2
• Filed: 10/07/2013
• Issued: 10/20/2015
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Xia, Haitao, Zhang, Fan, Li, Shu, Xiao, Jun
• Primary Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US14/047,423
• Publication Number:
  US 20150089330A1
• Time in Patent Office: 743 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/1128 Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
• CPC Class Codes: H03M 13/1142 using trapping sets
• CPC Class Codes: H03M 13/3723 using means or methods for the initialisation of the decoder
• CPC Class Codes: H03M 13/3746 with iterative decoding
• CPC Class Codes: H03M 13/6337 Error control coding in combination with channel estimation

Abstract

Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, estimating a voltage associated with the data in the data set corresponding to the critical location, calculating soft information corresponding to the critical location based at least in part on the estimated voltage, and re-applying the data decoding algorithm to the data set guided by the soft information to yield an updated decoded output.

Claims

1. A data processing system, the system comprising:

a solid state memory device; and

a data processing circuit to access a data set from the solid state memory device, the data processing circuit including;

a limited location re-read request circuit operable to identify a subset of elements of the data set derived from the solid state memory device exhibiting an increased likelihood of error, wherein identifying the subset of elements of the data set is based at least in part on selecting, up to a predetermined number of locations, one or more locations from the elements in the data set exhibiting the highest voltage variances from a first location to a subsequent location;

a soft information calculation circuit operable to calculate soft information indicating a probability that one or more elements of a data set derived from the solid state memory device represent data originally stored to the solid state memory device; and

a data decoding circuit operable to apply a data decoding algorithm to the data set derived from the solid state memory device guided by the soft information.

2. The data processing system of claim 1, wherein the data decoding algorithm is a low density parity check decoding algorithm.

3. The data processing system of claim 1, wherein identifying the subset of elements of the data set derived from the solid state memory device exhibiting an increased likelihood of error is based at least in part on an indicator selected from a group comprising:

one or more locations up to the predetermined number of locations selected from the elements in the data set that have the most number of bit modifications occurring during application of the data decoding algorithm,

one or more locations up to the predetermined number of locations selected from the elements in the data set associated with the most number of unsatisfied parity check equations, and

a location in the data set associated with a trapping set.

4. The data processing system of claim 1, wherein the data processing circuit is further operable to cause the identified subset of elements of the data set to be re-read using different threshold values applied to the solid state memory device to yield a number of re-read values, and to estimate a voltage stored by the solid state memory device for each of the identified subset of elements of the data set.

5. The data processing system of claim 4, wherein the soft information calculation circuit is operable to calculate the soft information based at least in part on the estimated voltage stored by the solid state memory device for each of the identified subset of elements of the data set.

6. The data processing system of claim 1, wherein the solid state memory device is operable to provide a voltage corresponding to at least one element of a data set accessible from the solid state memory device.

7. The data processing system of claim 6, wherein the soft information calculation circuit is operable to calculate the soft information based at least in part on the voltage corresponding to the at least one element of a data set accessible from the solid state memory device.

8. The data processing system of claim 1, wherein the data processing circuit is implemented as part of an integrated circuit.

9. The data processing system of claim 1, wherein the data processing circuit and the solid state memory device are implemented on the same integrated circuit.

10. The data processing system of claim 1, wherein the solid state memory device includes a number of flash memory cells.

11. The data processing system of claim 10, wherein each of the flash memory cells is able to hold a charge distinguishable as two bits of data.

12. The data processing system of claim 10, wherein the flash memory cells are NAND flash memory cells.

13. A method for recovering data, the method comprising:

accessing a data set from a solid state storage device;

using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output;

determining whether the decoded output converges, wherein the decoded output includes at least one error;

upon determining the decoded output fails to converge, identifying at least one critical location in the data set, wherein identifying the at least one critical location in the data set is based at least in part on selecting, up to a predetermined number of locations, one or more locations from the elements in the data set exhibiting the highest voltage variances from a first location to a subsequent location;

estimating a voltage associated with the data in the data set corresponding to the critical location;

calculating soft information corresponding to the critical location based at least in part on the estimated voltage; and

re-applying the data decoding algorithm to the data set guided by the soft information to yield an updated decoded output.

14. The method of claim 13, wherein the data decoding algorithm is a low density parity check decoding algorithm.

15. The method of claim 13, wherein identifying the at least one critical location in the data set is based at least in part on an indicator selected from a group comprising:

one or more locations up to the predetermined number of locations selected from the elements in the data set that have the most number of bit modifications occurring during application of the data decoding algorithm,

one or more locations up to the predetermined number of locations selected from the elements in the data set associated with the most number of unsatisfied parity check equations, and

a location in the data set associated with a trapping set.

16. The method of claim 13, wherein estimating the voltage associated with the data in the data set corresponding to the critical location includes re-accessing the data from the critical location using different threshold values applied to the solid state memory device to yield a number of re-read values, and estimating the voltage based upon the different threshold values and corresponding re-read values.

17. The method of claim 16, wherein the soft information is calculated based at least in part on the estimated voltage and a defined performance metric of the solid state storage device.

18. An electronic device, the electronic device including:

a storage system including;

a solid state memory device; and

a data processing circuit to access a data set from the solid state memory device, the data processing circuit including;

a limited location re-read request circuit to identify at least one critical location in the data set, wherein identifying the at least one critical location in the data set is based at least in part on selecting, up to a predetermined number of locations, one or more locations from the elements in the data set exhibiting the highest voltage variances from a first location to a subsequent location;

a soft information calculation circuit operable to calculate soft information indicating a probability that one or more elements of a data set derived from the solid state memory device represent data originally stored to the solid state memory device;

a data decoding circuit operable to apply a data decoding algorithm to the data set derived from the solid state memory device guided by the soft information; and

an application system operable to perform a defined function using data accessed from the storage system.

19. The electronic device of claim 18, wherein:

identifying the at least one critical location from the elements of the data set is based at least in part on an indicator selected from a group comprising;

one or more locations up to the predetermined number of locations selected from the elements in the data set that have the most number of bit modifications occurring during application of the data decoding algorithm,

one or more locations up to the predetermined number of locations selected from the elements in the data set associated with the most number of unsatisfied parity check equations, and

a location in the data set associated with a trapping set; and

the data processing circuit is further operable to cause the identified subset of elements of the data set to be re-read using different threshold values applied to the solid state memory device to yield a number of re-read values, and to estimate a voltage stored by the solid state memory device for each of the identified subset of elements of the data set, and wherein the soft information calculation circuit is operable to calculate the soft information based at least in part on the estimated voltage stored by the solid state memory device for each of the identified subset of elements of the data set.