Error recovery within integrated circuit

• US 9,164,842 B2
• Filed: 06/25/2013
• Issued: 10/20/2015
• Est. Priority Date: 03/20/2003
• Status: Expired due to Fees

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Flautner, Krisztian, Austin, Todd Michael, Blaauw, David Theodore, Mudge, Trevor Nigel, Bull, David
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Ahmed, Enam
• Application Number:
  US13/926,213
• Publication Number:
  US 20140013178A1
• Time in Patent Office: 847 Days
• Field of Search: 714/799
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/0706 the processing taking place on a specific hardware platform or in a specific software environment
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware

Abstract

An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Claims

1. An integrated circuit for performing data processing, said integrated circuit comprising:

a latch configured to receive and to store a signal value;

an error detector configured to detect errors in operation of said integrated circuit by detecting a late arriving transition in said signal value received by said latch;

error-repair circuitry configured to repair errors in operation of said integrated circuit

a plurality of processing stages, a processing stage output signal from at least one processing stage being supplied as a processing stage input signal to a following processing stage, wherein said at least one processing stage comprises;

processing logic configured to perform a processing operation upon at least one processing stage input value to generate a processing logic output signal;

a non-delayed latch configured to capture a non-delayed value of said processing logic output signal at a non-delayed capture time, said non-delayed value being supplied to said following processing stage as said processing stage output signal following said non-delayed capture time; and

a delayed latch configured to capture a delayed value of said processing logic output signal at a delayed capture time later than said non-delayed capture time;

wherein said error detector comprises a comparator configured to compare said non-delayed value and said delayed value to detect a change in said processing logic output signal following said non-delayed capture time indicative of said processing logic not having finished said processing operation at said non-delayed capture time; and

said error-repair logic is configured, when said comparator detects said change, to perform an error-repair operation suppressing use of said non-delayed value by said following processing stage.

2. An integrated circuit as claimed in claim 1, wherein said errors in operation arise from an operational parameter of said integrated circuit being outside a limit permitting error-free operation.

3. An integrated circuit as claimed in claim 2, wherein said one or more operational parameters include one or more of:

a power supply voltage;

a clock frequency of a clock signal; and

a body bias voltage.

4. An integrated circuit as claimed in claim 1, comprising a meta-stability detector configured to detect meta-stability in said non-delayed value and trigger said error-repair logic to suppress use of said non-delayed value if found to be meta-stable.

5. An integrated circuit as claimed in claim 1, wherein when said comparator detects said change, said error-repair logic is configured to replace said non-delayed value with said delayed value as said processing stage output signal.

6. An integrated circuit as claimed in claim 5, wherein supply of said delayed value to said following processing stage forces forward progress through processing operations.

7. An integrated circuit as claimed in claim 5, wherein a minimum processing time taken for said processing operation is greater than a time separating said delayed capture time from said non-delayed capture time such that said delayed value is not influenced by a processing operation performed upon different input values.

8. An integrated circuit as claimed in claim 7, wherein said processing logic includes one or more delay elements to ensure said minimum processing time is exceeded.

9. An integrated circuit as claimed in claim 1, wherein said integrated circuit is configured to operate with one or more operational parameters to produce a finite non-zero error rate within said integrated circuit.

10. A method of operating an integrated circuit for performing data processing, said method comprising the steps of:

receiving and storing a signal value with a latch;

detecting errors in operation of said integrated circuit by detecting a late arriving transition in said signal value received by said latch;

at least one processing stage performing a processing operation upon at least one processing stage input value to generate a processing logic output signal and capturing a non-delayed value of said processing logic output signal at a non-delayed capture time, said non-delayed value being supplied to a following processing stage as a processing stage output signal following said non-delayed capture time; and

capturing a delayed value of said processing logic output signal at a delayed capture time later than said non-delayed capture time,

wherein the detecting errors includes comparing said non-delayed value and said delayed value to detect a change in said processing logic output signal following said non-delayed capture time indicative of said processing logic not having finished said processing operation at said non-delayed capture time; and

wherein when said change is detected, performing an error-repair operation suppressing use of said non-delayed value by said following processing stage.

11. A method as claimed in claim 10, wherein said latch comprises a non-delayed latch clocked by a non-delayed clock signal and said error detector comprises a delayed latch associated with said non-delayed latch and clocked by a delayed clock signal to prevent errors in signal.

12. A method as claimed in claim 10, wherein said error detector comprises a transition detector configured to detect a transition within said signal value occurring with a predetermined time window.

13. A method as claimed in claim 10, wherein said errors in operation arise from an operational parameter of said integrated circuit being outside a limit permitting error-free operation.

14. A method as claimed in claim 10, wherein said one or more operational parameters include one or more of:

a power supply voltage;

a clock frequency of a clock signal; and

a body bias voltage.