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Error recovery within integrated circuit

  • US 9,164,842 B2
  • Filed: 06/25/2013
  • Issued: 10/20/2015
  • Est. Priority Date: 03/20/2003
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit for performing data processing, said integrated circuit comprising:

  • a latch configured to receive and to store a signal value;

    an error detector configured to detect errors in operation of said integrated circuit by detecting a late arriving transition in said signal value received by said latch;

    error-repair circuitry configured to repair errors in operation of said integrated circuita plurality of processing stages, a processing stage output signal from at least one processing stage being supplied as a processing stage input signal to a following processing stage, wherein said at least one processing stage comprises;

    processing logic configured to perform a processing operation upon at least one processing stage input value to generate a processing logic output signal;

    a non-delayed latch configured to capture a non-delayed value of said processing logic output signal at a non-delayed capture time, said non-delayed value being supplied to said following processing stage as said processing stage output signal following said non-delayed capture time; and

    a delayed latch configured to capture a delayed value of said processing logic output signal at a delayed capture time later than said non-delayed capture time;

    wherein said error detector comprises a comparator configured to compare said non-delayed value and said delayed value to detect a change in said processing logic output signal following said non-delayed capture time indicative of said processing logic not having finished said processing operation at said non-delayed capture time; and

    said error-repair logic is configured, when said comparator detects said change, to perform an error-repair operation suppressing use of said non-delayed value by said following processing stage.

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