Writing data to solid state drives

• US 9,164,892 B2
• Filed: 07/30/2012
• Issued: 10/20/2015
• Est. Priority Date: 07/30/2012
• Status: Expired due to Fees

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Oh, Hyun Oh
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US13/977,262
• Publication Number:
  US 20140032822A1
• Time in Patent Office: 1,177 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies

Abstract

Technologies and implementations for writing data to a solid state drive are generally disclosed.

Claims

1. A method to write data into a memory, comprising:

at a memory control module, receiving data to be written to a target page of the memory, wherein the target page comprises a plurality of memory cells including a first memory cell and a last memory cell;

determining a number of erase operations performed on the target page of the memory;

determining a writing direction as either a forward direction or a backward direction, based at least in part on the determined number of erase operations performed on the target page, wherein the forward direction writes data from the first memory cell of the page toward the last memory cell of the page and the backward direction writes data from the last memory cell of the page toward the first memory cell; and

writing the received data to the target page of the memory in the determined writing direction.

2. The method of claim 1, wherein writing the received data to the target page of the memory in the determined writing direction comprises:

determining a first address value of a first memory cell of the target page of the memory; and

writing the received data starting from the determined first address value.

3. The method of claim 1, wherein writing the received data comprises writing the received data in the forward direction when the determined number of erase operations corresponds to an even number.

4. The method of claim 1, wherein writing the received data comprises writing the received data in the backward direction when the determined number of erase operations corresponds to an odd number.

5. The method of claim 2, wherein determining the first address value of the first memory cell of the target page of the memory comprises:

determining the first address value as a lowest address value corresponding to the target page when the determined number of erase operations corresponds to an even number; and

determining the first address value as a highest address value corresponding to the target page when the determined number of erase operations corresponds to an odd number.

6. The method of claim 2, wherein determining the first address value of the first memory cell of the target page of the memory comprises:

determining a starting memory cell within the target page based in part upon the number of erase operations performed on the page and a modulo operation; and

determining the first address value of the first memory cell of the target page as an address value corresponding to the determined starting memory cell.

7. The method of claim 2, wherein writing the received data in the backward direction comprises:

writing a first portion of the received data to the first memory cell of the target page associated with the first address value;

determining a second address value of a second memory cell of the target page to write a second portion of the received data, by decrementing the first address value;

writing a second portion of the received data to the second memory cell associated with the second address value; and

writing each remaining portion of the received data to subsequent memory cells of the target page, wherein the address of each subsequent memory cell is determined by decrementing an address value of a previous memory cell.

8. The method of claim 1, wherein receiving data to be written to the target page of the memory comprises receiving data to be written to a target page of a solid state drive (SSD) storage device.

9. The method of claim 1, wherein receiving data to be written to the target page of the memory comprises receiving data to be written to the target page of the memory at a memory control module having a flash translation layer (FTL).

10. The method of claim 1, wherein determining the number of erase operations performed on the target page of the memory comprises determining the number of erase operations performed on the target page of the memory as an erasure count associated with a logical block, wherein the target page of the memory is part of the logical block.

11. A method to read data from a memory, comprising:

at a memory control module, receiving a request to read data from a target page of the memory, wherein the target page comprises a plurality of memory cells including a first memory cell and a last memory cell;

determining a writing direction as either a forward direction or a backward direction, wherein the writing direction is based at least in part on a number of erase operations performed on the target page, wherein the forward direction writes data from the first memory cell of the page toward the last memory cell of the page and the backward direction writes data from the last memory cell of the page toward the first memory cell; and

reading data from the target page of the memory in the determined writing direction.

12. The method of claim 11, wherein determining the writing direction as either a forward direction or a backward direction comprises:

determining a number of erase operations performed on the target page of the memory;

determining the writing direction as forward when the number of erase operations are even; and

determining the writing direction as backward when the number of erase operations are odd.

13. The method of claim 11, wherein reading data from the target page of the memory in the determined writing direction comprises:

determining a first address value of a first memory cell of the target page of the memory; and

reading data starting from the determined first address value.

14. The method of claim 13, wherein determining the first address value of the first memory cell of the target page of the memory comprises:

determining the first address value as a lowest address value corresponding to the target page when the determined number of erase operations corresponds to an even number; and

determining the first address value as a highest address value corresponding to the target page when the determined number of erase operations corresponds to an odd number.

15. The method of claim 13, wherein determining the first address value of the first memory cell of the target page of the memory comprises:

determining a starting memory cell within the target page based in part upon the number of erase operations performed on the page and a modulo operation; and

determining the first address value of the first memory cell of the target page as an address value corresponding to the determined starting memory cell.

16. The method of claim 13, wherein reading data from the target page of the memory in the determined writing direction comprises:

reading a first portion of the data to the first memory cell of the target page associated with the first address value;

determining a second address value of a second memory cell of the target page to read a second portion of the data, by decrementing the first address value;

reading a second portion of the data to the second memory cell associated with the second address value; and

reading each remaining portion of the data to subsequent memory cells of the target page, wherein the address of each subsequent memory cell is determined by decrementing an address value of a previous memory cell.

17. A machine-readable non-transitory medium having stored therein instructions that, in response to execution by one or more processors, operatively enable a memory control module to:

determine a number of erase operations performed on a target page of the memory, wherein the target page comprises a plurality of memory cells including a first memory cell and a last memory cell;

determine a writing direction as either a forward direction or a backward direction, based at least in part on the determined number of erase operations performed on the target page; and

write data to the target page of the memory in the determined writing direction, starting from a first memory cell of the target page of the memory.

18. The machine-readable non-transitory medium of claim 17, wherein the stored instructions, in response to execution by one or more processors, operatively enable the memory control module to:

determine a first address value of a first memory cell of the target page of the memory; and

write the data starting from the determined first address value.

19. The machine-readable non-transitory medium of claim 17, wherein the stored instructions, in response to execution by one or more processors, operatively enable the memory control module to write the data in the forward direction when the determined number of erase operations corresponds to an even number.

20. The machine-readable non-transitory medium of claim 17, wherein the stored instructions, in response to execution by one or more processors, operatively enable the memory control module to write the data in the backward direction when the determined number of erase operations corresponds to an odd number.

21. The machine-readable non-transitory medium of claim 18, wherein the stored instructions, in response to execution by one or more processors, operatively enable the memory control module to:

determine the first address value as a lowest address value corresponding to the target page when the determined number of erase operations corresponds to an even number; and

determine the first address value as a highest address value corresponding to the target page when the determined number of erase operations corresponds to an odd number.

22. A computing system, comprising:

a memory;

a memory control module to the memory and configured to determine a number of erase operations performed on a target page of the memory, wherein the target page comprises a plurality of memory cells including a first memory cell and a last memory cell, and to determine a starting address value of the first memory cell of the target page and a writing direction as either a forward direction or a backward direction, based at least in part upon the determined number of erase operations performed on the target page, wherein the forward direction writes data from the first memory cell of the page toward the last memory cell of the page and the backward direction writes data from the last memory cell of the page toward the first memory cell; and

write circuitry, coupled to the memory and to the memory control module, to write data to the target page starting from the starting address value determined by the memory control module and in the writing direction.

23. The computing system of claim 22, wherein to determine the starting address value, the memory control module is configured to determine a remainder resulting from a division of the determined number of erase operations by a particular number, and to obtain the starting address value at least in part from a division of a size of the target page by the determined remainder.

24. The computing system of claim 22, wherein the memory control module is configured to read data starting from the determined starting address value.

25. The computing system of claim 22, wherein to determine the writing direction as either the forward direction or the backward direction, the memory control module is configured to determine the writing direction as forward when the number of erase operations are even and determine the writing direction as backward when the number of erase operations are odd.