Linear to physical address translation with support for page attributes

• US 9,164,917 B2
• Filed: 08/08/2014
• Issued: 10/20/2015
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: Intel Corporation
• Inventors: Falik, Ohad, Friedman, Ben-Zion, Doweck, Jacob, Weissmann, Eliezer, Crossland, James B
• Primary Examiner(s): Tseng, Cheng-Yuan
• Assistant Examiner(s): Talukdar, Arvind
• Application Number:
  US14/455,147
• Publication Number:
  US 20140351554A1
• Time in Patent Office: 438 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/507 using speculative control
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/684 TLB miss handling
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/342 Extension of operand address space

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Claims

1. A computing system comprising:

a modem;

a random access memory;

an I/O device;

a processor comprising;

a plurality of registers;

at least one translation look aside buffer, wherein the at least one translation look aside buffer is to include a plurality of entries, wherein at least one entry is to include a physical address and a plurality of attributes associated with the physical address;

a page miss handler to perform a table walk; and

a physical address return register, wherein the physical address return register is a 64-bit register,

wherein the processor is to receive an instruction to translate a virtual address to a first physical address, wherein the instruction is a kernel level privileged instruction, and

wherein the instruction is to cause the processor, when in a 64-bit mode, to;

translate the virtual address to the first physical address;

store the first physical address translated from the virtual address in the physical address return register; and

store at least one attribute associated with the first physical address translated from the virtual address in the physical address return register.

2. The computing system of claim 1, wherein the at least one attribute comprises an indication of whether a fault occurred during the translation of the virtual address to the first physical address.

3. The computing system of claim 1, wherein the at least one attribute comprises a caching policy indication.

4. The computing system of claim 1, wherein the at least one attribute comprises a protection level.

5. The computing system of claim 1, wherein the instruction is to cause the processor to translate the virtual address to the first physical address as if a write is performed for the instruction.

6. The computing system of claim 1, wherein the physical address return register is a register dedicated to storing physical addresses and associated attributes.

7. The computing system of claim 1, wherein the instruction is to operate at a higher privilege level than an application.

8. The computing system of claim 1, wherein the instruction is to cause the processor to translate the virtual address to the first physical address without accessing data at the first physical address in a memory hierarchy.

9. A computing system comprising:

a modem;

a random access memory;

an I/O device; and

a processor comprising;

a plurality of registers;

at least one translation look aside buffer, wherein the at least one translation look aside buffer is to include a plurality of entries, wherein at least one entry is to include a physical address and a plurality of attributes associated with the physical address;

a page miss handler to perform a table walk; and

a physical address return register, wherein the physical address return register is a 64-bit register,

wherein the processor is to receive an instruction to translate a virtual address to a first physical address, wherein the instruction is a kernel level privileged instruction, and

wherein the instruction is to cause the processor, when in a 64-bit mode, to;

start to translate the virtual address to the first physical address;

store an indication that a fault occurred in the physical address return register; and

store a level at which the fault occurred in the physical address return register.

10. The computing system of claim 9, wherein the instruction is to cause the processor not to take an exception when the fault occurred.

11. The computing system of claim 9, wherein the physical address return register is a register dedicated to storing a physical address translated from a virtual address.

12. The computing system of claim 9, wherein the instruction is to cause the processor to start to translate the virtual address to the first physical address as if a write is to be performed for the instruction.

13. The computing system of claim 9, wherein the instruction is to operate at a higher privilege level than applications.