Memory system with calibrated data communication

• US 9,164,933 B2
• Filed: 02/03/2015
• Issued: 10/20/2015
• Est. Priority Date: 10/19/1999
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared LeVan, Donnelly, Kevin S., Sidiropoulos, Stefanos, Stark, Donald C., Horowitz, Mark A., Yu, Leung, Vu, Roxanne, Kim, Jun, Garlepp, Bruno W., Ho, Tsyr-Chyang, Lau, Benedict Chung-Kwong
• Primary Examiner(s): Nguyen, Brian D
• Application Number:
  US14/613,276
• Publication Number:
  US 20150169478A1
• Time in Patent Office: 259 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Claims

1. A memory sub-system comprising:

a plurality of flash memory devices coupled to a bus; and

a set of bus transceiver devices coupled to the bus, each individual bus transceiver device in the set comprising;

an interface circuit for coupling the bus transceiver device to a memory controller;

circuitry to receive a signal to individually address the individual bus transceiver device by the memory controller;

a reference voltage register to store a device-specific value; and

a receiver circuit to receive a data signal transmitted by the memory controller to the individual bus transceiver device;

wherein the device-specific value stored in the reference voltage register of each individual bus transceiver device controls a reference voltage used by the corresponding receiver circuit when receiving the data signal transmitted by the memory controller to the individual bus transceiver device.

2. The memory sub-system of claim 1, wherein the device-specific value stored in the reference voltage register of each individual bus transceiver device is determined during a calibration mode of operation of the individual bus transceiver device.

3. The memory sub-system of claim 1, wherein each individual bus transceiver device in the set of bus transceiver devices includes a write offset register to store a device-specific offset value corresponding to a receive timing adjustment;

and

wherein the receiver circuit of each bus transceiver device is configured to sample the received data signal with a timing offset corresponding to the device-specific offset value stored in the write offset register.

4. The memory sub-system of claim 3, further comprising one of a flash memory device and a dynamic random access memory (DRAM) device.

5. The memory sub-system of claim 1, wherein each individual bus transceiver device in the set of bus transceiver devices includes:

a read offset register to store a device-specific offset value corresponding to a transmit timing adjustment; and

a transmit circuit to transmit a data signal from the individual bus transceiver device to the memory controller with a timing offset corresponding to the device-specific offset value stored in the read offset register.

6. The memory sub-system of claim 5, wherein the device-specific offset value stored in the read offset register is determined during a calibration mode of operation of each individual bus transceiver device.

7. The memory sub-system of claim 5, wherein each individual bus transceiver device in the set of bus transceiver devices includes a delay-locked-loop (DLL) or phase-locked-loop (PLL) circuit operable to produce a transmit clock signal coupled to a clock input of the transmit circuit, or a receive clock signal coupled to a clock input of the receiver circuit.

8. The memory sub-system of claim 1, wherein each individual bus transceiver device in the set of bus transceiver devices includes calibration circuitry operable in a calibration mode and comprising a phase detector, the phase detector of a respective individual bus transceiver device comprising:

a first input to receive a clock signal,

a second input to receive a calibration sequence via a signal path associated with transmitting write data between the memory controller and the respective individual bus transceiver device, and

an output to provide phase data representing a phase difference between the clock signal and the received calibration sequence; and

wherein the respective individual bus transceiver device further includes a transmitter to transmit the phase data to the memory controller.

9. The memory sub-system of claim 1, wherein each individual bus transceiver device in the set of bus transceiver devices includes calibration circuitry operable in a calibration mode, the calibration circuitry including a first input to receive a clock signal and a second input to receive a calibration sequence via a signal path associated with transmitting write data between the memory controller and the memory sub-system.

10. The memory sub-system of claim 9, wherein the calibration sequence is a data pattern received from the memory controller.

11. The memory sub-system of claim 1, wherein each individual bus transceiver device in includes a delay-locked-loop (DLL) or phase-locked-loop (PLL) circuit operable to produce a receive clock signal coupled to a clock input of the receiver circuit.

12. A method of operating a memory sub-system having a set of bus transceiver devices and a plurality of flash devices, the method comprising:

individually addressing, by a memory controller, each individual bus transceiver device in the set of bus transceiver devices;

storing, in each individual bus transceiver device of the set of bus transceiver devices, a device-specific value in a reference voltage register of the bus transceiver of the individual bus transceiver device; and

at a respective individual bus transceiver device in the set of bus transceiver devices, receiving a data signal, the data signal transmitted by the memory controller to the respective individual bus transceiver device;

wherein receiving the data signal includes receiving the data signal using a reference voltage controlled by the device-specific value stored in the reference voltage register of the respective individual bus transceiver device.

13. The method of claim 12, further including, storing the device-specific value in the reference voltage register of each individual bus transceiver device during a calibration mode of operation.

14. The method of claim 12, wherein each individual bus transceiver device in the set of bus transceiver devices includes a write offset register to store a device-specific offset value corresponding to a receive timing adjustment;

and

the method includes sampling the data signal with a timing offset corresponding to the device-specific offset value stored in the write offset register of each respective individual bus transceiver device.

15. The method of claim 14, including storing the device-specific offset value in the write offset voltage register of each bus transceiver device during a calibration mode of operation.

16. The method of claim 14, including internally generating, within each individual bus transceiver device, a receive clock signal using a delay-locked-loop (DLL) or phase-locked-loop (PLL) circuit, and providing the receive clock signal to an input of the device'"'"'s receiver circuit.

17. The method of claim 12, wherein each individual bus transceiver device in the set of bus transceiver devices includes a transmit circuit and a read offset register to store a device-specific offset value corresponding to a transmit timing adjustment;

and

the method further includes, using the transmit circuit of a respective individual bus transceiver device, transmitting a data signal to the memory controller according to a timing offset corresponding to the device-specific offset value stored in the read offset register of the respective individual bus transceiver device.

18. The method of claim 17, including storing the device-specific value in the read offset register of each individual bus transceiver device during a calibration mode of operation.

19. The method of claim 12, wherein each individual bus transceiver device in the set of bus transceiver devices includes calibration circuitry operable in a calibration mode, the method further including, at each of the bus transceiver devices, while operating in the calibration mode, receiving a calibration sequence via a signal path associated with transmitting write data between the memory controller and the memory sub-system, generating phase data representing a phase difference between a clock signal and the received calibration sequence, and transmitting the phase data to the memory controller.

20. An apparatus comprising

a plurality of flash memory devices coupled to a bus;

and

a set of transceiver devices coupled to the bus, each individual bus transceiver device in the set comprising;

an interface circuit for coupling the bus transceiver device to a memory controller;

a reference voltage register to store a device-specific value; and

a receiver circuit to receive a data signal transmitted by the memory controller to the individual bus transceiver device;

wherein the device-specific value stored in the reference voltage register of each individual bus transceiver device controls a reference voltage used by the corresponding receiver circuit when receiving the data signal transmitted by the memory controller to the individual bus transceiver device.