Memory system with calibrated data communication
First Claim
1. A memory sub-system comprising:
- a plurality of flash memory devices coupled to a bus; and
a set of bus transceiver devices coupled to the bus, each individual bus transceiver device in the set comprising;
an interface circuit for coupling the bus transceiver device to a memory controller;
circuitry to receive a signal to individually address the individual bus transceiver device by the memory controller;
a reference voltage register to store a device-specific value; and
a receiver circuit to receive a data signal transmitted by the memory controller to the individual bus transceiver device;
wherein the device-specific value stored in the reference voltage register of each individual bus transceiver device controls a reference voltage used by the corresponding receiver circuit when receiving the data signal transmitted by the memory controller to the individual bus transceiver device.
1 Assignment
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Accused Products
Abstract
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
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Citations
20 Claims
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1. A memory sub-system comprising:
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a plurality of flash memory devices coupled to a bus; and a set of bus transceiver devices coupled to the bus, each individual bus transceiver device in the set comprising; an interface circuit for coupling the bus transceiver device to a memory controller; circuitry to receive a signal to individually address the individual bus transceiver device by the memory controller; a reference voltage register to store a device-specific value; and a receiver circuit to receive a data signal transmitted by the memory controller to the individual bus transceiver device; wherein the device-specific value stored in the reference voltage register of each individual bus transceiver device controls a reference voltage used by the corresponding receiver circuit when receiving the data signal transmitted by the memory controller to the individual bus transceiver device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of operating a memory sub-system having a set of bus transceiver devices and a plurality of flash devices, the method comprising:
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individually addressing, by a memory controller, each individual bus transceiver device in the set of bus transceiver devices; storing, in each individual bus transceiver device of the set of bus transceiver devices, a device-specific value in a reference voltage register of the bus transceiver of the individual bus transceiver device; and at a respective individual bus transceiver device in the set of bus transceiver devices, receiving a data signal, the data signal transmitted by the memory controller to the respective individual bus transceiver device; wherein receiving the data signal includes receiving the data signal using a reference voltage controlled by the device-specific value stored in the reference voltage register of the respective individual bus transceiver device. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. An apparatus comprising
a plurality of flash memory devices coupled to a bus; - and
a set of transceiver devices coupled to the bus, each individual bus transceiver device in the set comprising; an interface circuit for coupling the bus transceiver device to a memory controller; a reference voltage register to store a device-specific value; and a receiver circuit to receive a data signal transmitted by the memory controller to the individual bus transceiver device; wherein the device-specific value stored in the reference voltage register of each individual bus transceiver device controls a reference voltage used by the corresponding receiver circuit when receiving the data signal transmitted by the memory controller to the individual bus transceiver device.
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Specification