Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system

• US 9,164,937 B2
• Filed: 03/24/2014
• Issued: 10/20/2015
• Est. Priority Date: 02/05/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Larson, Douglas A., Cronin, Jeffrey J
• Primary Examiner(s): DOAN, DUC T
• Application Number:
  US14/223,443
• Publication Number:
  US 20140207993A1
• Time in Patent Office: 575 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Claims

1. A system, comprising:

a controller;

a plurality of memory modules coupled to the controller by a bi-directional data bus, and each memory module of the plurality of memory modules coupled to a respective other memory module of the plurality of memory modules by the bi-directional data bus, wherein each memory module of the plurality of memory modules is configured to process memory commands issued from the controller, wherein a first memory module of the plurality of memory modules includes bypass circuitry configured to capture write data associated with a write command passing to a third memory module of the plurality of memory modules, and wherein the first memory module is further configured to allow read data associated with a read command to return from a second memory module of the plurality of memory modules before allowing the captured write data to continue on to the third memory module, and wherein the bypass circuit is further configured to put an output buffer in a high impedance state responsive to storing write data from the bi-directional data bus while read data is transferred over the bi-directional data bus between first and second data bus interfaces of the memory module of the plurality of memory modules.

2. The system of claim 1, wherein the controller is configured to issue the write command associated with the write data after issuing the read command associated with the read data and prior to the controller receiving the read data.

3. The system of claim 2, wherein the controller is further configured to provide the write data on an interface coupled to the first memory module after issuing the read command and before receiving the read data.

4. The system of claim 1, further comprising a processor coupled to the controller.

5. The system of claim 1, wherein each memory module of the plurality of memory modules comprises a respective plurality of memory devices.

6. The system of claim 1, wherein the plurality of memory modules are coupled in series.

7. The system of claim 1, wherein each memory module of the plurality of memory modules is coupled to a respective other memory module of the plurality of memory modules through a respective bi-directional interface.

8. The system of claim 1, wherein the first memory module is further downstream than the second memory module relative to the controller and the second memory module is further downstream than the third memory module relative to the controller.

9. The system of claim 1, wherein the plurality of memory modules are configured in a point-to-point arrangement.

10. A system, comprising:

a controller configured to provide write data to and receive read data from a plurality of memory modules;

a bi-directional data bus coupled to the controller and configured to transfer read data in a first direction and configured to transfer write data in a second direction opposite of the first direction; and

each memory module of the plurality of memory modules including;

a first data bus interface coupled to the bi-directional data bus;

a second data bus interface coupled to the bi-directional data bus; and

a bypass circuit coupled to the first and second data bus interfaces and configured to store write data from the bi-directional data bus while read data is transferred over the bi-directional data bus between the first and second data bus interfaces in the first direction and restore write data to the bi-directional data bus in the second direction when the read data has finished transmitting, wherein the bypass circuit comprises;

a write data input buffer with an input coupled to the second data bus interface and configured to buffer the write data;

a bypass register with an input coupled to an output of the write data input buffer and configured to store the write data;

a multiplexer with a first input coupled to the output of the write data input buffer and a second input coupled to an output of the bypass register and configured to couple the second input to an output based on a control signal;

a write data output buffer with an input coupled to the output of the multiplexer and an output coupled to the first data bus interface, wherein the write data output buffer is configured to provide the write data to the first data bus interface, and further configured to be put into a high impedance state based on an enable signal; and

bypass select logic coupled to the multiplexer and the write data output buffer, wherein the bypass select logic is configured to provide the control signal and the enable signal based on the read data being transferred over the bi-directional data bus between the first and second data bus interfaces in the first direction.

11. The system of claim 10, wherein the memory module of the plurality of memory modules further includes control logic configured to control the bypass circuit responsive to a bypass signal.

12. The system of claim 11, wherein the control logic receives bypass commands from the memory controller.

13. The system of claim 10, wherein the bypass circuit is configured to store the write data in a register while read data is transferred over the bi-directional data bus between the first and second data bus interfaces in the first direction.

14. The system of claim 10, wherein the bypass circuit is configured to couple an output of an input buffer to an input of an output buffer to restore write data to the data bidirectional bus in the second direction when the read data has finished transmitting.

15. A system, comprising:

a controller configured to provide write data and receive read data;

a bi-directional data bus coupled to the controller and configured to transfer read data in a first direction and configured to transfer write data in a second direction opposite of the first direction; and

each module of a plurality of memory modules including;

a first data bus interface coupled to the bi-directional data bus;

a second data bus interface coupled to the bi-directional data bus; and

a bypass circuit coupled to the first and second data bus interfaces and configured to store write data from the bi-directional data bus, while read data is transferred overwrite data to the data bus in the second direction when the read data has finished transmitting, wherein the bypass circuit is configured to put an output buffer in a high impedance state responsive to storing write data from the bi-directional data bus while read data is transferred over the bi-directional data bus between the first and second data bus interfaces.

16. A system, comprising:

a memory controller configured to provide write data associated with a write command; and

a first memory module coupled to the controller by a bi-directional data bus and configured to receive the write data and to store the write data, the first memory module coupled to a second memory module by the bi-directional data bus and configured to receive read data associated with a read command from the second memory module, the first memory module configured to provide the read data to the controller and to provide the write data to the second memory responsive to providing the read data to the controller, wherein the first memory controller includes a bypass circuit configured to store write data from the bi-directional data bus while read data is transferred over the data bus between first and second data bus interfaces of the first memory in a first direction and restore write data to the data bus in a second direction when the read data has finished transmitting, wherein the bypass circuit is configured to put an output buffer in a high impedance state responsive to storing write data from the bi-directional data bus while read data is transferred over the bi-directional data bus between the first and second data bus interfaces.

17. The system of claim 16, wherein the memory controller is configured to provide the write command after the read command and before receiving the read data.

18. The system of claim 16, wherein the first memory is configured to store the write data in a data bypass circuit.

19. The system of claim 18, wherein the memory controller is configured to cause the first memory to store the write data in the bypass circuit using a bypass enable control signal.

20. The system of claim 16, wherein the read command is associated with the second memory and the write command is associated with a third memory.