Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

• US 9,164,952 B2
• Filed: 09/24/2013
• Issued: 10/20/2015
• Est. Priority Date: 03/22/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Master, Paul L., Hogenauer, Eugene, Scheuermann, Walter J.
• Primary Examiner(s): Partridge, William B
• Application Number:
  US14/035,067
• Publication Number:
  US 20140122764A1
• Time in Patent Office: 756 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Claims

1. An adaptive computing engine comprising:

a first configurable computational unit including a first plurality of heterogeneous computational elements, the first plurality of heterogeneous computational elements including an adder, a register, and a function generator, the first plurality of heterogeneous computational elements coupled to each other via a first interconnection network to configure interconnections between the computational elements in response to configuration information to perform a first function;

a second configurable computational unit for performing digital signal processing functions, the second computational unit including a second plurality of heterogeneous computational elements, the second plurality of heterogeneous computational elements including at least one multiplier computational element and at least one adder computational element, the second plurality of heterogeneous computational elements coupled to each other via a second interconnection network to configure the interconnections between the second plurality of heterogeneous computational elements in response to configuration information to perform a digital signal processing function; and

a third interconnection network coupled between the first and second configurable computational units.

2. The adaptive computing engine of claim 1, wherein the third interconnection network sends the configuration information to the first and second interconnection networks.

3. The adaptive computing engine of claim 1, wherein the first and second interconnection networks include multiplexers coupled to the first and second pluralities of heterogeneous computational elements, the multiplexers routing data between the first and second pluralities of heterogeneous computational elements.

4. The adaptive computing engine of claim 3 wherein the first and second interconnection networks route control signals to control the multiplexers to switch data to the plurality of heterogeneous computational elements.

5. The adaptive computing engine of claim 1, wherein the interconnections of the first interconnection network to the first and second pluralities of heterogeneous computational elements have a greater density than the interconnections of the third interconnection network to the configurable computational units.

6. The adaptive computing engine of claim 1, wherein the first function is a logic function, arithmetic function or a register function.

7. The adaptive computing engine of claim 1, wherein the digital signal processing function is one of a fixed point arithmetic, floating point arithmetic, filtering, or transformation functions.

8. The adaptive computing engine of claim 1, wherein the function performed by the configurable computational unit is bit level manipulation and the digital signal processing function is bit or word level manipulation.

9. The adaptive computing engine of claim 1, wherein the adder computational elements are one of a plurality of adder computational elements, and wherein the multiplier computational elements are of a plurality of multiplier computational elements and wherein the second plurality of heterogeneous computational elements includes a plurality of arithmetic logical computational elements.

10. The adaptive computing engine of claim 9, wherein the second interconnection network changes the interconnections between the second plurality of heterogeneous computational elements to perform another digital signal processing function by bypassing at least one of the plurality of adder computational elements, or at least one of the plurality of multiplier computational elements or at least one of the plurality of arithmetic logical computational elements.

11. An adaptive integrated circuit comprising:

a first plurality of heterogeneous computational elements, the first plurality of heterogeneous computational elements including an adder, a register, and a function generator, the first plurality of heterogeneous computational elements coupled to each other via a first interconnection network to configure interconnections between the heterogeneous computational elements in response to configuration information to perform a first function;

a second plurality of heterogeneous computational elements, the second plurality of heterogeneous computational elements including a multiplier computational element and an adder computational element, the second plurality of heterogeneous computational elements coupled to each other via a second interconnection network to configure the interconnections between the second plurality of heterogeneous computational elements in response to configuration information to perform a digital signal processing function; and

a third interconnection network coupled between at least some of the first and second heterogeneous computational elements.

12. The adaptive integrated circuit of claim 11, wherein the third interconnection network sends the configuration information to the first and second interconnection networks.

13. The adaptive integrated circuit of claim 11, wherein the first and second interconnection networks include multiplexers coupled to the first and second pluralities of heterogeneous computational elements, the multiplexers routing data between the first and second pluralities of heterogeneous computational elements.

14. The adaptive integrated circuit of claim 13 wherein the first and second interconnection networks route control signals to control the multiplexers to switch data to the plurality of heterogeneous computational elements.

15. The adaptive integrated circuit of claim 11, wherein the first function is a logic function, arithmetic function or a register function.

16. The adaptive integrated circuit of claim 11, wherein the digital signal processing function is one of a fixed point arithmetic, floating point arithmetic, filtering, or transformation functions.

17. An adaptive computing system comprising:

a plurality of configurable computational units, each of the plurality of configurable computational units having multiple computational elements including an adder, a register, and a function generator, the computational elements coupled to each other via an interconnection network to configure interconnections between the computational elements in response to configuration information to perform a first function; and

a plurality of configurable digital signal processing units, each the configurable digital signal processing units having multiple heterogeneous computational elements including a multiplier computational element and an adder computational element and an interconnection network coupled to the heterogeneous computational elements to configure the interconnections between the heterogeneous computational elements in response to configuration information to perform a digital signal processing function, wherein each of the plurality of configurable digital signal processing units is in communication with one of the plurality of configurable computational units.

18. The adaptive computing engine of claim 17, further comprising another interconnection network coupled to the plurality of configurable computational units and plurality of configurable digital signal processing units, the another interconnection network sending the configuration information to the interconnection networks of the plurality of configurable computational units and the plurality of digital signal processing units.

19. The adaptive computing engine of claim 17, wherein the interconnections of the interconnection networks of the plurality of configurable computational units and the plurality of digital signal processing units have a greater density than the interconnections of the another interconnection network to the configurable computational units and the digital signal processing units.

20. The adaptive computing engine of claim 17, wherein the interconnection networks include multiplexers coupled to the computational elements, the multiplexers routing data between the pluralities of computational elements.

21. The adaptive computing engine of claim 17, wherein the first function is a logic function, arithmetic function or a register function.

22. The adaptive computing engine of claim 17, wherein the digital signal processing function is one of a fixed point arithmetic, floating point arithmetic, filtering, or transformation functions.