RFID tag dynamically adjusting clock frequency

• US 9,165,170 B1
• Filed: 05/11/2015
• Issued: 10/20/2015
• Est. Priority Date: 03/13/2008
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Gutnik, Vadim, Cooper, Scott A., Hyde, John D., Stanford, Theron
• Primary Examiner(s): McNally, Kerri
• Assistant Examiner(s): OBINIYI, PAULSON IDOWU
• Application Number:
  US14/709,331
• Time in Patent Office: 162 Days
• Field of Search: 340 101- 106, 3405721-5729, 235375-385
• US Class Current: 1/1
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/016 Synchronisation of sensing process
• CPC Class Codes: G06K 7/10207 parameter settings related to power consumption of the interrogator
• CPC Class Codes: H04Q 2213/13095 PIN / Access code, authentication
• CPC Class Codes: H04Q 2213/13214 Clock signals

Abstract

An RFID tag is configured to adjust its current clock frequency to conserve tag power while receiving a reader signal and/or backscattering a signal. The tag may determine whether to adjust its current clock frequency based on one or more timing parameters, which may be determined from a reader command and/or from a signal to be backscattered. The counting rate and/or limit of a tag counter and/or the power supplied to a tag component may also be adjusted. The current tag clock frequency may be adjusted during the signal reception/backscattering process and optionally restored once the process is completed.

Claims

1. A method for a Radio Frequency Identification (RFID) tag to dynamically adjust a frequency of a clock oscillator, the method comprising:

receiving, from a reader, values for two or more of a TRcal, an RTcal, a DR, a Tari, and a BLF;

calculating a first symbol duration based on the received values;

comparing the calculated first symbol duration to a symbol decision threshold;

determining, based on the comparison, whether the frequency can be reduced;

if so then;

adjusting a counting rate of a counter;

reducing the frequency by adjusting at least one of a divide ratio, bias, resistance, capacitance, and inductance of the clock oscillator;

calculating a second symbol duration based on the reduced frequency; and

if necessary to meet error limits of a protocol, then adjusting at least one of the second symbol duration and the reduced frequency such that the second symbol duration meets the error limits; and

if not then;

not adjusting the counting rate of the counter, and

not reducing the frequency.

2. The method of claim 1, wherein adjusting the resistance comprises at least one of switching a resistor in or out and adjusting an adjustable resistor.

3. The method of claim 1, wherein adjusting the capacitance comprises at least one of switching a capacitor in or out and adjusting an adjustable capacitor.

4. The method of claim 1, wherein adjusting the inductance comprises at least one of switching an inductor in or out and adjusting an adjustable inductor.

5. The method of claim 1, further comprising subsequently restoring the frequency.

6. The method of claim 1, further comprising adjusting a limit of a tag counter.

7. A Radio Frequency Identification (RFID) integrated circuit (IC) configured to dynamically adjust a frequency of a clock oscillator, the IC comprising:

a transceiver configured to communicate with a reader; and

a processing block coupled to the transceiver and configured to;

receive, from the reader, values for two or more of a TRcal, an RTcal, a DR, a Tari, and a BLF;

calculate a first symbol duration based on the received values;

compare the calculated first symbol duration to a symbol decision threshold;

determine, based on the comparison, whether the frequency can be reduced;

if so, then;

adjust a counting rate of a counter;

reduce the frequency by adjusting at least one of a divide ratio, bias, resistance, capacitance, and inductance of the clock oscillator;

calculate a second symbol duration based on the reduced frequency; and

if necessary to meet error limits of a protocol, then adjust at least one of the second symbol duration and the reduced frequency such that the second symbol duration meets the error limits; and

if not then;

not adjusting the counting rate of the counter; and

not reducing the frequency.

8. The IC of claim 7, wherein the resistance is adjusted by at least one of switching a resistor in or out and adjusting an adjustable resistor.

9. The IC of claim 7, wherein the capacitance is adjusted by at least one of switching a capacitor in or out and adjusting an adjustable capacitor.

10. The IC of claim 7, wherein the inductance is adjusted by at least one of switching an inductor in or out and adjusting an adjustable inductor.

11. The IC of claim 7, wherein the processing block is further configured to subsequently restore the frequency.

12. The IC of claim 7, wherein the processing block is further configured to adjust a limit of a tag counter.

13. A Radio Frequency Identification (RFID) tag comprising:

an antenna; and

an RFID integrated circuit coupled to the antenna and configured to;

receive, using the antenna, values for two or more of a TRcal, an RTcal, a DR, a Tari, and a BLF;

calculate a first symbol duration based on the received values;

compare the calculated first symbol duration to a symbol decision threshold;

determine, based on the comparison, whether a frequency of a clock oscillator can be reduced;

if so, then;

adjust a counting rate of a counter;

reduce the frequency by adjusting at least one of a divide ratio, bias, resistance, capacitance, and inductance of the clock oscillator;

calculate a second symbol duration based on the reduced frequency; and

if necessary to meet error limits of a protocol, then adjust at least one of the second symbol duration and the reduced frequency such that the second symbol duration meets the error limits; and

if not then;

not adjusting the counting rate of the counter; and

not reducing the frequency.

14. The tag of claim 13, wherein the resistance is adjusted by at least one of switching a resistor in or out and adjusting an adjustable resistor.

15. The tag of claim 13, wherein the capacitance is adjusted by at least one of switching a capacitor in or out and adjusting an adjustable capacitor.

16. The tag of claim 13, wherein the inductance is adjusted by at least one of switching an inductor in or out and adjusting an adjustable inductor.

17. The tag of claim 13, wherein the RFID integrated circuit is further configured to subsequently restore the frequency.

18. The tag of claim 13, wherein the RFID integrated circuit is further configured to adjust a limit of a tag counter.