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Graphics processing unit with a texture return buffer and a texture queue

  • US 9,165,396 B2
  • Filed: 02/26/2013
  • Issued: 10/20/2015
  • Est. Priority Date: 02/26/2013
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a texture return buffer having a plurality of slots for storing texture values, wherein the slots of the texture return buffer are addressable by a thread; and

    a texture unit coupled to the texture return buffer, wherein the texture unit is configured to allocate a slot of the texture return buffer when the texture unit generates a texture value,wherein the texture unit comprises;

    a texture filtering unit configured to filter sampled texture data to generate the texture value,a texture address unit configured to generate one or more physical addresses based on one or more texture coordinates associated with a texture operation, anda texture latency FIFO (First-in, First-out) coupled to the texture address unit and configured to buffer texture operations while sampled texture data is fetched from locations in memory corresponding to the one or more physical addresses.

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