Graphics processing unit with a texture return buffer and a texture queue

• US 9,165,396 B2
• Filed: 02/26/2013
• Issued: 10/20/2015
• Est. Priority Date: 02/26/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Tarjan, David
• Primary Examiner(s): Sajous, Wesner
• Application Number:
  US13/778,031
• Publication Number:
  US 20140240329A1
• Time in Patent Office: 966 Days
• Field of Search: 345/418, 345/582, 345501-503, 345505-506, 345/522, 345530-531, 345/543, 345/545, 345/549, 345/552, 345/554, 345/557, 345/558, 345564-565, 382/276, 382/285, 382/260, 382/305, 382303-304, 382/307, 711/3, 711/100, 711/113, 711/125, 711/173, 711/202, 711/209, 711/214, 711/221
• US Class Current: 1/1
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G06T 2210/52 Parallel processing

Abstract

A processor and a system are provided for performing texturing operations. The processor includes a texture return buffer having a plurality of slots for storing texture values and one or more texture units coupled to the texture return buffer. Each of the slots of the texture return buffer are addressable by a thread. Each texture unit is configured to allocate a slot of the texture return buffer when the texture unit generates a texture value.

Claims

1. A processor comprising:

a texture return buffer having a plurality of slots for storing texture values, wherein the slots of the texture return buffer are addressable by a thread; and

a texture unit coupled to the texture return buffer, wherein the texture unit is configured to allocate a slot of the texture return buffer when the texture unit generates a texture value,

wherein the texture unit comprises;

a texture filtering unit configured to filter sampled texture data to generate the texture value,

a texture address unit configured to generate one or more physical addresses based on one or more texture coordinates associated with a texture operation, and

a texture latency FIFO (First-in, First-out) coupled to the texture address unit and configured to buffer texture operations while sampled texture data is fetched from locations in memory corresponding to the one or more physical addresses.

3. The processor of claim 1, wherein an instruction set of the processor includes instructions having operands that reference slots in the texture return buffer.

4. The processor of claim 3, wherein an instruction to read a texture value from the texture return buffer comprises a last use bit that indicates whether a particular slot of the texture return buffer storing the texture value is free to be allocated for a different texture value.

5. The processor of claim 1, further comprising a texture identifier mapping table that associates one or more texture identifiers with corresponding entry identifiers of the texture return buffer, wherein an entry identifier specifies a particular slot of the texture return buffer.

6. The processor of claim 5, wherein the one or more texture identifiers comprise an unsigned integer.

7. The processor of claim 5, further comprising a cache, and wherein the texture identifier mapping table is implemented in a portion of the cache.

8. The processor of claim 1, further comprising a register file, and wherein the texture return buffer is implemented in a portion of the register file.

9. The processor of claim 1, further comprising a cache, and wherein a texture queue is implemented in a portion of the cache.

10. The processor of claim 9, wherein the texture queue comprises a plurality of circular FIFOs, and wherein each circular FIFO corresponds to a thread that is an instance of a shader program.

11. The processor of claim 1, further comprising a cache, and wherein the texture return buffer is implemented in a portion of the cache.

12. The processor of claim 1, wherein the processor comprises two or more texture units configured to process a plurality of texture operations in parallel.

13. The processor of claim 12, wherein the processor comprises a graphics processing unit.

2. A system comprising:

a processor comprising;

a texture return buffer having a plurality of slots for storing texture values, wherein the slots of the texture return buffer are addressable by a thread; and

a texture unit coupled to the texture return buffer, wherein the texture unit is configured to allocate a slot of the texture return buffer when the texture unit generates a texture value,

wherein the texture unit comprises;

a texture filtering unit configured to filter sampled texture data to generate the texture value,

a texture address unit configured to generate one or more physical addresses based on one or more texture coordinates associated with a texture operation, and

a texture latency FIFO (First-in, First-out) coupled to the texture address unit and configured to buffer texture operations while sampled texture data is fetched from memory locations corresponding to the one or more physical addresses.

14. A system comprising:

a processor comprising;

a texture return buffer having a plurality of slots for storing texture values, wherein the slots of the texture return buffer are addressable by a thread; and

a texture unit coupled to the texture return buffer, wherein the texture unit is configured to allocate a slot of the texture return buffer when the texture unit generates a texture value,

wherein the texture unit comprises a texture filtering unit configured to filter sampled texture data to generate the texture value and allocate a slot of the texture return buffer to store the texture value.

15. The system of claim 14, the processor further comprising a plurality of core processing units configured to execute different threads of a shader program, wherein the texture return buffer is accessible by the plurality of core processing units.

16. The system of claim 14, wherein the processor comprises a graphics processing unit.

17. The system of claim 16, the system further comprising:

a central processing unit; and

a memory storing a shader program and a driver that generates texture operations for processing by the texture unit in response to instructions included in the shader program.