Method of using a PMOS pass gate

• US 9,165,640 B1
• Filed: 07/17/2014
• Issued: 10/20/2015
• Est. Priority Date: 07/12/2011
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Liu, Jun, Ratnakumar, Albert, Rahim, Irfan, Xiang, Qi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/333,871
• Time in Patent Office: 460 Days
• Field of Search: 365/156, 365/189.05, 365/185.05
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

A method that includes using a PMOS pass gate to couple a first line to a second line, where a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell, is described. In one implementation, the PMOS pass gate has a negative threshold voltage. In one implementation, the first line and the second line are respectively first and second interconnect lines of an IC.

Claims

1. A method comprising:

using a p-channel metal oxide semiconductor (PMOS) pass gate to couple a first line to a second line, wherein a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell.

2. The method of claim 1, wherein the PMOS pass gate has a negative threshold voltage.

3. The method of claim 1, wherein the PMOS pass gate has a non-negative threshold voltage, the method further comprising:

applying a negative bias voltage to the memory cell,

wherein a negative gate voltage causes the PMOS pass gate to be in an ON state.

4. The method of claim 1, wherein data stored in the memory cell controls a state of the PMOS pass gate.

5. The method of claim 1, wherein the PMOS pass gate is a routing PMOS pass gate.

6. The method of claim 1, wherein the memory cell includes a first inverter and a second inverter coupled to the first inverter, wherein each of the first and second inverters is a complementary metal oxide semiconductor (CMOS) inverter including a n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a PMOS transistor, and wherein the NMOS transistor and the PMOS transistor of the CMOS inverter are thick oxide transistors.

7. The method of claim 1, wherein the memory cell is a memory cell in configuration random access memory (RAM).

8. The method of claim 1, wherein there is no well separation between the PMOS pass gate and transistors in the memory cell.

9. The method of claim 1, wherein the first line and the second line are respectively first and second lines of a look up table (LUT).

10. The method of claim 1, wherein the first and second lines are respectively first and second interconnect lines of an integrated circuit.

11. The method of claim 1, wherein the first and second lines are respectively first and second interconnect lines of a programmable logic device.

12. A method comprising:

using a p-channel metal oxide semiconductor (PMOS) pass gate to couple a first line to a second line, wherein a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell in a configuration random access memory (RAM),

wherein the PMOS pass gate is a routing PMOS pass gate, further wherein data stored in the memory cell determines a state of the PMOS pass gate.

13. The method of claim 12, wherein the PMOS pass gate has a negative threshold voltage.

14. The method of claim 12, wherein the memory cell includes a first inverter and a second inverter coupled to the first inverter, wherein each of the first and second inverters is a complementary metal oxide semiconductor (CMOS) inverter including a n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a PMOS transistor, and wherein the NMOS transistor and the PMOS transistor of the CMOS inverter are thick oxide transistors.

15. The method of claim 12, wherein the PMOS pass gate has a non-negative threshold voltage, the method further comprising:

applying a negative bias voltage to the memory cell,

wherein a negative gate voltage causes the PMOS pass gate to be in an ON state.

16. The method of claim 12, wherein the first line and the second line are respectively first and second lines of a look up table (LUT).

17. The method of claim 12, wherein the first and second lines are respectively first and second interconnect lines of an integrated circuit (IC).

18. The method of claim 17, wherein the IC is a programmable logic device.

19. A method comprising:

using a p-channel metal oxide semiconductor (PMOS) pass gate to couple a first interconnect line to a second interconnect line of an integrated circuit (IC), wherein a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell in a configuration random access memory (RAM),

wherein the memory cell includes a first inverter and a second inverter coupled to the first inverter, wherein each of the first and second inverters is a complementary metal oxide semiconductor (CMOS) inverter including a n-channel metal oxide semiconductor (NMOS) transistor coupled in series to a PMOS transistor, and wherein the NMOS transistor and the PMOS transistor of the CMOS inverter are thick oxide transistors,

wherein the PMOS pass gate is a routing PMOS pass gate, wherein the PMOS pass gate has a negative threshold voltage, and further wherein data stored in the memory cell determines a state of the PMOS pass gate.

20. The method of claim 19, wherein the IC is a programmable logic device.