Fault bits scrambling memory and method thereof

• US 9,165,684 B2
• Filed: 03/31/2014
• Issued: 10/20/2015
• Est. Priority Date: 07/09/2013
• Status: Active Grant

• Current Assignee: National Taiwan University of Science and Technology
• Original Assignee: National Taiwan University of Science and Technology
• Inventors: Lu, Shyue-Kung, Jheng, Hao-Cheng
• Primary Examiner(s): Ton, David
• Application Number:
  US14/230,554
• Publication Number:
  US 20150019924A1
• Time in Patent Office: 568 Days
• Field of Search: 714/718
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

A fault bits scrambling memory and method thereof relate to a memory including at least one memory bank. The memory bank includes a memory module, a scrambling-logic unit, a self-testing unit and a scrambling code generating unit. The memory module includes a plurality of pages. Each page has a plurality of memory cells, and each memory cell has a physical address. The scrambling logic unit receives a scrambling code and the physical address to generate a mapping address by logical calculation, and outputs the mapping address to the memory module. The self-testing unit detects the faulty memory cells of each page. The scrambling code generating unit is applied to generate the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.

Claims

1. A fault bits scrambling memory, comprising:

at least a memory bank, each memory bank comprising a memory module, the memory module comprising a plurality of pages, each page comprising a plurality of memory cells, each memory cell having a physical address;

a scrambling logic unit, receiving a scrambling code and the physical address to generate a mapping address by logical computation, and outputting the mapping address to the memory module so that an external module accesses the data of the memory cell corresponding to the mapping address according to the physical address;

a self-testing unit, detecting faulty memory cells of each page to generate a faulty information; and

a scrambling code generating unit, receiving the faulty information and generating the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.

2. The fault bits scrambling memory according to claim 1, wherein each page stores an error correction code, an error correcting algorithm is based on the error correction code to repair the faulty memory cells of the page, and the maximum number of the faulty memory cells to be repairable is the maximum tolerance.

3. The fault bits scrambling memory according to claim 1, wherein the physical address comprises a first column address and a first row address, the scrambling logic unit comprises a column scrambling logic circuit and a row scrambling logic circuit, the column scrambling logic circuit receives the scrambling code and the first column address to generate a second column address, the row scrambling logic circuit receives the scrambling code and the first row address to generate a second row address, the second column address and the second row address are combined to form the mapping address.

4. The fault bits scrambling memory according to claim 3, wherein the scrambling logic unit further comprises;

a column scrambling code register, located between the scrambling code generating unit and the column scrambling logic circuit to store the scrambling code; and

a row scrambling code register, located between the scrambling code generating unit and the row scrambling logic circuit to store the scrambling code.

5. The fault bits scrambling memory according to claim 3, wherein the scrambling code comprises a column scrambling code and a row scrambling code, the scrambling logic unit further comprises:

a column scrambling code register, located between the scrambling code generating unit and the column scrambling logic circuit to store the column scrambling code; and

a row scrambling code register, located between the scrambling code generating unit and the row scrambling logic circuit to store the row scrambling code.

6. A fault bits scrambling method, applicable to a memory having a plurality of pages, each page comprising a plurality of memory cells, each memory cell having a physical address, the fault bits scrambling method comprising:

detecting faulty memory cells of each page to generate a faulty information;

generating a scrambling code;

executing a logical computation with the scrambling code and each physical address to individually obtain a mapping address; and

verifying the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.

7. The fault bits scrambling method according to claim 6, further comprising:

generating an error correction code based on the data stored in the memory cells of the same page according to an error correcting algorithm;

storing the error correction code in the page; and

executing the error correcting algorithm according to the error correction code to repair the data stored in the faulty memory cell upon one of the pages having the faulty memory cell.

8. The fault bits scrambling method according to claim 6, further comprising:

judging whether the number of the faulty memory cells exceeds the maximum tolerance, if yes, executing a built-in redundancy analysis algorithm to repair the data stored in the faulty memory cells.

9. The fault bits scrambling method according to claim 6, further comprising:

accessing the data of the memory cell corresponding to the mapping address according to the physical address.