Electronic devices having semiconductor memory units and method for fabricating the same

• US 9,165,787 B2
• Filed: 03/07/2014
• Issued: 10/20/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Kang, Jung-Hyun
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/201,696
• Publication Number:
  US 20140269005A1
• Time in Patent Office: 592 Days
• Field of Search: 365/148, 365/163, 365/51, 365/63, 438/95, 438/133
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 2213/56 Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/061 Shaping switching materials
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

The disclosed technology provides an electronic device and a fabrication method thereof. An electronic device according to an implementation of the disclosed technology may include: a first interlayer insulating layer formed over a substrate; first and second contact plugs passing through the first interlayer insulating layer to contact the substrate and alternately arranged to cross each other; a variable resistance element formed over the first interlayer insulating layer and coupled to the first contact plug; a second interlayer insulating layer formed over an entire structure including the first interlayer insulating layer; a third contact plug passing through the second interlayer insulating layer so as to be coupled to the variable resistance element, and a fourth contact plug passing through the second interlayer insulating layer so as to be contacted to the second contact plug; and conductive lines coupled to the third contact plug and the fourth contact plug, respectively.

Claims

1. An electronic device comprising a semiconductor memory unit which includes:

a substrate;

a first interlayer insulating layer formed over the substrate;

first and second contact plugs passing through the first interlayer insulating layer and located over the substrate, the first and second contact plugs alternately arranged to have a regular intervals from each other;

a variable resistance element formed over the first interlayer insulating layer and coupled to the first contact plug;

a second interlayer insulating layer formed over an entire structure including the first interlayer insulating layer, the variable resistance element, the first contact plug and the second contact plug;

a third contact plug passing through the second interlayer insulating layer so as to be coupled to the variable resistance element;

a fourth contact plug passing through the second interlayer insulating layer so as to be electrically connected to the second contact plug; and

conductive lines coupled to the third contact plug and the fourth contact plug, respectively.

2. The electronic device of claim 1, wherein the second and fourth contact plugs are arranged to overlap each other in a vertical direction.

3. The electronic device according to claim 1, further comprising a microprocessor which includes:

a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;

an operation unit configured to perform an operation based on a result that the control unit decodes the command; and

a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory unit is a part of the memory unit in the microprocessor.

4. The electronic device according to claim 1, further comprising a processor which includes:

a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;

a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and

a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,

wherein the semiconductor memory unit is a part of the cache memory unit in the processor.

5. The electronic device according to claim 1, further comprising a processing system which includes:

a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;

an auxiliary memory device configured to store a program for decoding the command and the information;

a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and

an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,

wherein the semiconductor memory unit is a part of the auxiliary memory device or the main memory device in the processing system.

6. The electronic device according to claim 1, further comprising a data storage system which includes:

a storage device configured to store data and conserve stored data regardless of power supply;

a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;

a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and

an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,

wherein the semiconductor memory unit is a part of the storage device or the temporary storage device in the data storage system.

7. The electronic device according to claim 1, further comprising a memory system which includes:

a memory configured to store data and conserve stored data regardless of power supply;

a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;

a buffer memory configured to buffer data exchanged between the memory and the outside; and

an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,

wherein the semiconductor memory unit is a part of the memory or the buffer memory in the memory system.

8. An electronic device comprising a semiconductor memory unit which includes:

a substrate;

a first interlayer insulating layer formed over the substrate;

first and second contact plugs passing through the first interlayer insulating layer and located over the substrate, the first and second contact plugs alternately arranged to have a regular intervals from each other;

a variable resistance element formed over the first interlayer insulating layer and coupled to the first contact plug;

a second interlayer insulating layer formed over an entire structure including the first interlayer insulating layer, the variable resistance element, the first contact plug and the second contact plug;

a third contact plug passing through the second interlayer insulating layer so as to be coupled to the variable resistance element;

a fourth contact plug passing through the second interlayer insulating layer so as to be coupled to the second contact plug; and

conductive lines coupled to the third contact plug and the fourth contact plug, respectively,

wherein the first and third contact plugs are arranged to overlap each other in a vertical direction.

9. The electronic device of claim 8, wherein the second and fourth contact plugs are arranged to overlap each other in a vertical direction.

10. The electronic device according to claim 8, further comprising a microprocessor which includes:

a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;

an operation unit configured to perform an operation based on a result that the control unit decodes the command; and

a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory unit is a part of the memory unit in the microprocessor.

11. The electronic device according to claim 8, further comprising a processor which includes:

a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;

a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and

a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,

wherein the semiconductor memory unit is a part of the cache memory unit in the processor.

12. The electronic device according to claim 8, further comprising a processing system which includes:

a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;

an auxiliary memory device configured to store a program for decoding the command and the information;

a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and

an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,

wherein the semiconductor memory unit is a part of the auxiliary memory device or the main memory device in the processing system.

13. The electronic device according to claim 8, further comprising a data storage system which includes:

a storage device configured to store data and conserve stored data regardless of power supply;

a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;

a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and

an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,

wherein the semiconductor memory unit is a part of the storage device or the temporary storage device in the data storage system.

14. The electronic device according to claim 8, further comprising a memory system which includes:

a memory configured to store data and conserve stored data regardless of power supply;

a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;

a buffer memory configured to buffer data exchanged between the memory and the outside; and

an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,

wherein the semiconductor memory unit is a part of the memory or the buffer memory in the memory system.

15. A method for fabricating an electronic device, comprising:

forming a first interlayer insulating layer over a substrate;

simultaneously forming a first contact plug and a second contact plug, which pass through the first interlayer insulating layer to be coupled the substrate and are alternately arranged to have a regular intervals from each other;

forming a variable resistance element over the first interlayer insulating layer which is coupled to the first contact plug;

forming a second interlayer insulating layer over an entire structure including the first interlayer insulating layer, the variable resistance element, the first contact plug and the second contact plug;

simultaneously forming a third contact plug and a fourth contact plug wherein the third contact plug passes through the second interlayer insulating layer so as to be coupled to the variable resistance element and the fourth contact plug passes through the second interlayer insulating layer to electrically connect to the second contact plug; and

forming conductive lines over the second interlayer insulating layer, the conductive lines being coupled to the third contact plug and the fourth contact plug, respectively.

16. The method of claim 15, wherein the simultaneously forming of the third contact plug and the fourth contact plugs and the simultaneously forming of the first contact plug and the second contact plug are performed by using the same mask.

17. The method of claim 15, wherein the simultaneously forming of the first contact plug and the second contact plug comprises:

forming a first negative photoresist layer on the first interlayer insulating layer;

forming a first photoresist pattern to have a line-type patterns by patterning the first negative photoresist layer through exposure and development processes;

forming a second negative photoresist layer on the first interlayer insulating layer and the first photoresist pattern;

forming a second photoresist pattern to have an opened diagonal island-shaped portions by patterning the second negative photoresist layer through exposure and development processes; and

etching the first interlayer insulating layer using hole patterns exposed by the first and second photoresist patterns.

18. The method of claim 17, wherein the forming of the first photoresist pattern comprises:

exposing a portion of the first negative photoresist layer; and

developing the remaining regions of the first negative photoresist layer that are not exposed to remove the remaining regions of the first negative photoresist layer,

wherein the remaining regions developed provide a space the first and second contact plugs are to be formed.

19. The method of claim 17, wherein the forming of the second photoresist pattern comprises:

exposing a portion of the second negative photoresist layer; and

developing the remaining regions of the second negative photoresist layer that are not exposed to remove the remaining regions of the second negative photoresist layer;

wherein the remaining regions developed provide a space that the third and fourth contact plugs are to be formed.

20. The method of claim 17, the forming of the second photoresist pattern comprises:

forming the non-exposed region inclined with respect to the non-exposed region of the first negative photoresist layer to form overlapping portion with the non-exposed region of the first negative photoresist layer; and

controlling an inclined angle such that the overlapping portions are not located in the same line in a transverse direction.

21. The method of claim 15, wherein the non-exposed region of the second negative photoresist layer include three portions overlapping with the non-exposed region of the first negative photoresist layer.