Making electrical components in handle wafers of integrated circuit packages

• US 9,165,793 B1
• Filed: 05/02/2014
• Issued: 10/20/2015
• Est. Priority Date: 05/02/2014
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Wang, Liang, Shen, Hong, Katkar, Rajesh
• Primary Examiner(s): Smith, Bradley K
• Application Number:
  US14/268,899
• Publication Number:
  US 20150318344A1
• Time in Patent Office: 536 Days
• Field of Search: 438/127, 438/381, 257/773
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/11 the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 25/115 the devices being arranged next to each other
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 : Electrodes
• CPC Class Codes: H01L 28/65 : comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1205 : Capacitor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16153 : Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]

Abstract

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Claims

1. A method for making an integrated circuit package, the method comprising:

providing a handle wafer having a first region and a second region, the first region at least partially defining a cavity within the handle wafer, the cavity defining the second region;

forming a capacitor in the first region of the handle wafer, the capacitor having a pair of electrodes, each electrode being electroconductively coupled to a corresponding one of a pair of electroconductive pads, at least one of which is disposed on a lower surface of the handle wafer in the first region thereof;

providing an interposer having an upper surface with an electroconductive pad and a semiconductor die disposed thereon, the die having an integrated circuit (IC) formed therein, the IC being electroconductively coupled to a redistribution layer (RDL) disposed on or within the interposer; and

bonding the lower surface of the handle wafer to the upper surface of the interposer such that the semiconductor die is disposed below or within the cavity of the handle wafer and the at least one electroconductive pad of the handle wafer is electroconductively bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

2. The method of claim 1, wherein the other one of the electroconductive pads of the handle wafer is disposed on an upper surface thereof.

3. The method of claim 1, wherein the forming of the capacitor comprises:

making a recess in a lower surface of the first region, the recess having an interior surface;

creating a first electroconductive layer on or in the interior surface of the recess;

coating the first electroconductive layer with a layer of a dielectric;

depositing a second electroconductive layer on the layer of dielectric; and

,

electrically coupling each of the first and second conductive layers to a corresponding one of the electroconductive pads.

4. The method of claim 3, wherein the forming of the capacitor comprises forming at least one upstanding rod or ridge on a floor of the recess.

5. The method of claim 3, wherein the forming of the capacitor comprises forming an array of rods or ridges on a floor of the recess.

6. The method of claim 3, wherein the creating of the first electroconductive layer comprises doping the first region of the handle wafer, doping the interior surface of the recess, or depositing a first layer of a metal on the interior surface of the recess.

7. The method of claim 6, wherein the depositing comprises one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), electroless plating and/or sputtering.

8. The method of claim 3, wherein at least one of the coating of the first electroconductive layer with a layer of a dielectric and the depositing of the second electroconductive layer comprises one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), vapor phase deposition and/or sputtering.

9. The method of claim 1, wherein a volume is defined between the semiconductor die and interior walls of the cavity, and further comprising:

forming a channel in the handle wafer, the channel communicating between the volume and an exterior surface of the handle wafer; and

injecting a filler into the volume through the channel.

10. The method of claim 9, wherein the filler comprises an epoxy or a thermal interface material.

11. The method of claim 1, further comprising

forming a capacitor below the upper surface of the interposer, the capacitor having a pair of electrodes electrically coupled to corresponding ones of a pair of electroconductive pads, at least one of which comprises the electroconductive pad disposed on the upper surface of the interposer,

whereby one of the pair of electrodes of the capacitor of the handle wafer is electrically coupled to one of the pair of electrodes of the capacitor of the interposer.

12. An integrated circuit package made in accordance with the method of claim 1.

13. An integrated circuit package made in accordance with the method of claim 11.

14. An integrated circuit package, comprising:

a first substrate having a first region and a second region, the first region at least partially defining a cavity within the substrate, the cavity defining the second region;

a capacitor formed in the first region of the first substrate, the capacitor comprising a layer of a dielectric sandwiched between a pair of electroconductive plates, each plate being electroconductively coupled to a corresponding one of a pair of electroconductive pads, at least one of which is disposed on the lower surface of the first substrate in the first region thereof; and

,

a second substrate having an upper surface with an electroconductive pad and a semiconductor die disposed thereon, the die having an integrated circuit (IC) formed therein, the IC being electroconductively coupled to a redistribution layer (RDL) disposed on or within the second substrate, wherein

the lower surface of the first substrate is bonded to the upper surface of the second substrate such that the die is disposed below or within the cavity and the at least one electroconductive pad of the first substrate is electroconductively bonded to the electroconductive pad of the second substrate in a metal-to-metal bond.

15. The integrated circuit package of claim 14, wherein at least one of the first and second substrates comprises a semiconductor, glass, ceramic, or a polymer.

16. The integrated circuit package of claim 14, wherein at least one of the pair of electroconductive plates comprises a doped semiconductor, tantalum (Ta), copper (Cu), titanium (Ti), titanium nitride (TiN), silver (Ag), gold (Au), aluminum (Al), chromium (Cr), palladium (Pd), platinum (Pt), Ruthenium (Ru), osmium (Os), or rhodium (Rh).

17. The integrated circuit package of claim 14, wherein the dielectric comprises Parylene, silicon oxide (SiO₂), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), titanium dioxide (TiO2), or strontium titanate (SrTiO3).

18. The integrated circuit package of claim 14, wherein the first region of the first substrate comprises a doped semiconductor.

19. The integrated circuit package of claim 14, wherein the metal-to-metal bond comprises an aluminum-to-aluminum (AL-to-AL) bond, a gold-to-gold (Au—

Au) bond or a copper-to-copper (Cu—

Cu) bond.

20. The integrated circuit package of claim 14, wherein

the second substrate further includes a capacitor disposed below the upper surface thereof, the capacitor having a pair of electroconductive plates, each plate being electroconductively coupled to a corresponding one of a pair of electroconductive pads, at least one of which comprises the electroconductive pad disposed on the upper surface of the second substrate, whereby one of the pair of electroconductive plates of the capacitor of the first substrate is electrically coupled to one of the pair of electroconductive plates of the capacitor of the second substrate, and

the capacitor of the first substrate is disposed above and in a stacked alignment with the capacitor of the second substrate.