ESD protection circuit

• US 9,165,891 B2
• Filed: 04/26/2013
• Issued: 10/20/2015
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Esd Protection Circuit, Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Liang, Yung-Chih, Yeh, Chih-Ting
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US13/871,281
• Publication Number:
  US 20130234199A1
• Time in Patent Office: 907 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

One embodiment of the disclosure provides an electrostatic discharge protection circuit. The electrostatic discharge protection circuit includes a p-type field effect transistor, a capacitance device and an n-type field effect transistor. The p-type field effect transistor has a source coupled to an input/output terminal, a gate coupled to a first node and a drain coupled to a second node. The capacitance device has a first terminal coupled to a first rail and a second terminal coupled to the first node. The n-type field effect transistor has a source coupled to the first rail, a gate coupled to the second node and a drain coupled to the first node.

Claims

1. An electrostatic discharge protection circuit, comprising:

a p-type field effect transistor, having a source coupled to an input/output terminal, a gate coupled to a first node and a drain coupled to a second node;

a capacitance device, having a first terminal coupled to a first rail and a second terminal coupled to the first node;

an n-type field effect transistor, having a source coupled to the first rail, a gate coupled to the second node and a drain coupled to the first node, wherein the p-type field effect transistor is formed on a first N-well, and the first N-well and the n-type field effect transistor are formed on a substrate;

a parasitic silicon controlled rectifier, wherein the parasitic silicon controlled rectifier is constructed by the source of the p-type field effect transistor, the first N-well, the substrate and the source of the n-type field effect transistor, and the parasitic silicon controlled rectifier further comprises a first control terminal coupled to the second node and/or a second control terminal coupled to the first node, wherein the parasitic silicon controlled rectifier is triggered by injecting current into the first control terminal and/or drawing current from the second control terminal.

2. The electrostatic discharge protection circuit as claimed in claim 1, further comprising a first resistor, having a first terminal coupled to a second rail and a second terminal coupled to the first node.

3. The electrostatic discharge protection circuit as claimed in claim 1, further comprising:

a first diode, having an anode coupled to the drain of the p-type field effect transistor and a cathode coupled to the second node; and

/or

a second diode, having an anode coupled to the first node and a cathode coupled to the drain of the n-type field effect transistor.

4. The electrostatic discharge protection circuit as claimed in claim 1, further comprises an additional diode having an anode coupled to the first rail and a cathode coupled to the input/output terminal.

5. The electrostatic discharge protection circuit as claimed in claim 1, wherein a parasitic diode formed between the input/output terminal and the second rail when a buck terminal of the p-type field effect transistor is coupled to the second rail.

6. The electrostatic discharge protection circuit as claimed in claim 1, further comprising a discharge device, having a first control terminal coupled to the second node and/or a second control terminal coupled to the first node, wherein the first control terminal and the second control terminal are arranged to trigger the discharge device.

7. The electrostatic discharge protection circuit as claimed in claim 1, further comprising a third diode, having an anode coupled to a parasitic silicon controlled rectifier or a control terminal of a discharge device and a cathode coupled to the first node.

8. The electrostatic discharge protection circuit as claimed in claim 7, further comprising a second resistor, having a first terminal coupled to the first rail and a second terminal coupled to the second node.

9. The electrostatic discharge protection circuit as claimed in claim 3, further comprising:

a first diode string, having an anode coupled to the cathode of the first diode and a cathode coupled to the second node; and

/or

a second diode string, having an anode coupled to the cathode of the second diode and a cathode coupled to the drain of the n-type field effect transistor.

10. The electrostatic discharge protection circuit as claimed in claim 1, wherein the capacitance device is a diode device, a plate capacitor or a MOS capacitor.

11. An electrostatic discharge protection circuit, comprising:

a p-type field effect transistor, having a source coupled to a first rail, a gate coupled to a first node and a drain coupled to a second node;

a capacitance device, having a first terminal coupled to a second rail and a second terminal coupled to the first node;

an n-type field effect transistor, having a source coupled to an input/output terminal, a gate coupled to the second node and a drain coupled to the first node, wherein the p-type field effect transistor is formed on a first N-well, and the first N-well and the n-type field effect transistor are formed on a substrate; and

a parasitic silicon controlled rectifier, wherein the parasitic silicon controlled rectifier is constructed by the source of the p-type field effect transistor, the first N-well, the substrate and the source of the n-type field effect transistor, and the parasitic silicon controlled rectifier further comprises a first control terminal coupled to the second node and/or a second control terminal coupled to the first node, wherein the parasitic silicon controlled rectifier is triggered by injecting current into the first control terminal and/or drawing current from the second control terminal.

12. The electrostatic discharge protection circuit as claimed in claim 11, further comprising a first resistor, having a first terminal coupled to the first rail and a second terminal coupled to the first node.

13. The electrostatic discharge protection circuit as claimed in claim 11, further comprising:

a first diode, having an anode coupled to the drain of the p-type field effect transistor and a cathode coupled to the second node; and

/or

a second diode, having an anode coupled to the first node and a cathode coupled to the drain of the n-type field effect transistor.

14. The electrostatic discharge protection circuit as claimed in claim 11, further comprises an additional diode having an anode coupled to the input/output terminal and a cathode coupled to the first rail.

15. The electrostatic discharge protection circuit as claimed in claim 11, wherein a parasitic diode formed between the input/output terminal and the second rail when a buck terminal of the n-type field effect transistor is coupled to the second rail.

16. The electrostatic discharge protection circuit as claimed in claim 11, further comprising a discharge device, having a first control terminal coupled to the second node and/or a second control terminal coupled to the first node, wherein the first control terminal and the second control terminal are arranged to trigger the discharge device.

17. The electrostatic discharge protection circuit as claimed in claim 11, further comprising a third diode, having an anode coupled to a parasitic silicon controlled rectifier or a control terminal of a discharge device and a cathode coupled to the first node.

18. The electrostatic discharge protection circuit as claimed in claim 17, further comprising a second resistor, having a first terminal coupled to the second rail and a second terminal coupled to the second node.

19. The electrostatic discharge protection circuit as claimed in claim 13, further comprising:

a first diode string, having an anode coupled to the cathode of the first diode and a cathode coupled to the second node; and

/or

a second diode string, having an anode coupled to the cathode of the second diode and a cathode coupled to the drain of the n-type field effect transistor.

20. The electrostatic discharge protection circuit as claimed in claim 11, wherein the capacitance device is a diode device, a plate capacitor or a MOS capacitor.

21. An electrostatic discharge protection circuit, comprising:

a p-type field effect transistor, having a source coupled to a first rail, a gate coupled to a first node and a drain coupled to a second node;

a capacitance device, having a first terminal coupled to a second rail and a second terminal coupled to the first node;

an n-type field effect transistor, having a source coupled to the second rail, a gate coupled to the second node and a drain coupled to the first node, wherein the p-type field effect transistor is formed on a first N-well, and the first N-well and the n-type field effect transistor are formed on a substrate;

a parasitic silicon controlled rectifier, wherein the parasitic silicon controlled rectifier is constructed by the source of the p-type field effect transistor, the first N-well, the substrate and the source of the n-type field effect transistor, and the parasitic silicon controlled rectifier further comprises a first control terminal coupled to the second node and a second control terminal coupled to the first node, wherein the parasitic silicon controlled rectifier is triggered by injecting current into the first control terminal and drawing current from the second control terminal.

22. The electrostatic discharge protection circuit as claimed in claim 21, further comprising:

a first diode, having an anode coupled to the drain of the p-type field effect transistor and a cathode coupled to the second node; and

/or

a second diode, having an anode coupled to the first node and a cathode coupled to the drain of the n-type field effect transistor.

23. The electrostatic discharge protection circuit as claimed in claim 21, further comprising a discharge device, having a first control terminal coupled to the second node and/or a second control terminal coupled to the first node, wherein the first control terminal and the second control terminal are arranged to trigger the discharge device.

24. The electrostatic discharge protection circuit as claimed in claim 21, wherein the capacitance device is a diode device, a plate capacitor or a MOS capacitor.

25. The electrostatic discharge protection circuit as claimed in claim 22, further comprising:

a first diode string, having an anode coupled to the cathode of the first diode and a cathode coupled to the second node; and

/or

a second diode string, having an anode coupled to the cathode of the second diode and a cathode coupled to the drain of the n-type field effect transistor.

26. An electrostatic discharge protection circuit, comprising:

a substrate, having a first contact point, a second contact point and a first n-type doped region;

a first N-well, formed in the substrate, having a third contact point coupled to a first rail;

a second n-type doped region, formed on the first N-well and coupled to the first rail; and

a third n-type doped region, formed on the first N-well and coupled to a first node;

a p-type field effect transistor, formed on the first N-well, comprising;

a first p-type doped region, formed on the first N-well and coupled to a second node;

a first gate, coupled to the first node; and

a second p-type doped region, formed on the first N-well and coupled to the first rail;

an n-type field effect transistor, formed on the substrate, comprising;

a second gate, coupled to the second node;

a fourth n-type doped region, formed on the substrate and coupled to a second rail; and

a fifth n-type doped region, formed on the substrate and coupled to the first node;

a capacitance device, having a first terminal coupled to the second rail and a second terminal coupled to the first node, wherein the second contact point is coupled to the second node, and the first contact point and the first n-type doped region are coupled to the second rail;

a first parasitic silicon controlled rectifier, wherein the first parasitic silicon controlled rectifier comprises the second p-type doped region of the p-type field effect transistor, the first N-well, the substrate and the first n-type doped region, wherein a first parasitic resistor is formed on the substrate by the second contact point and the first contact point;

a second parasitic silicon controlled rectifier, wherein the second parasitic silicon controlled rectifier comprises the third contact point, the first N-well, the substrate and the fourth n-type doped region of the n-type field effect transistor, wherein the third contact point is a fifth p-type doped region, wherein a second parasitic resistor is formed on the first N-well by the second n-type doped region and the third n-type doped region.

27. The electrostatic discharge protection circuit as claimed in claim 26, further comprising:

a second N-well, formed in the substrate;

a first diode, formed on the second N-well, comprising;

a sixth n-type doped region, formed on the second N-well and coupled to the second node; and

a third p-type doped region, formed on the second N-well and coupled to the first p-type doped region;

a third N-well, formed in the substrate; and

a second diode, formed on the third N-well, comprising;

a seventh n-type doped region, formed on the third N-well and coupled to the fifth n-type doped region; and

a fourth p-type doped region, formed on the third N-well and coupled to the first node.

28. The electrostatic discharge protection circuit as claimed in claim 26, wherein the second contact point is disposed between the second p-type doped region and the first n-type doped region, the third n-type doped region is disposed between the third contact point and the fourth n-type doped region.

29. The electrostatic discharge protection circuit as claimed in claim 28, wherein the first contact point is a sixth p-type doped region formed on the substrate, the second contact point is a seventh p-type doped region formed on the substrate, and a fourth contact point is an eighth n-type doped region formed on a fourth N-well.

30. The electrostatic discharge protection circuit as claimed in claim 26, wherein the capacitance device is a diode device.

31. The electrostatic discharge protection circuit as claimed in claim 30, wherein the diode device comprises at least one fourth N-well and the substrate, the fourth N-well includes the fourth contact point coupled to the first node, and the first terminal of the capacitance device is coupled to the second rail through the first contact point.