Semiconductor devices including stair step structures, and related methods
First Claim
1. A semiconductor device, comprising a memory array block defined by an elongated stack of continuous conductive tiers, the memory array block comprising a stair step structure positioned between longitudinal ends of the memory array block, the stair step structure defining contact regions for electrically contacting respective conductive tiers of the elongated stack of continuous conductive tiers, wherein the stair step structure is positioned longitudinally between a first portion of vertical strings of memory cells of the memory array block and a second portion of vertical strings of memory cells of the memory array block.
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Accused Products
Abstract
Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
41 Citations
29 Claims
- 1. A semiconductor device, comprising a memory array block defined by an elongated stack of continuous conductive tiers, the memory array block comprising a stair step structure positioned between longitudinal ends of the memory array block, the stair step structure defining contact regions for electrically contacting respective conductive tiers of the elongated stack of continuous conductive tiers, wherein the stair step structure is positioned longitudinally between a first portion of vertical strings of memory cells of the memory array block and a second portion of vertical strings of memory cells of the memory array block.
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8. A semiconductor device structure including a three-dimensional memory array, the semiconductor device structure comprising:
elongated memory array blocks laterally adjacent to one another, each of the memory array blocks comprising; a vertical stack of horizontal conductive tiers separated by electrically insulating material; a stair step structure defined by portions of the conductive tiers, the stair step structure positioned along a lateral side of the memory array block and between opposing lateral side surfaces of the memory array block for providing electrical access to respective conductive tiers of the vertical stack of horizontal conductive tiers; and electrically conductive access lines electrically coupling respective conductive tiers of the stair step structure to at least one control unit positioned under the vertical stack of horizontal conductive tiers. - View Dependent Claims (9, 10, 11)
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12. A semiconductor device comprising:
a three-dimensional memory array block elongated in a horizontal direction, the three-dimensional memory array block comprising; a vertical stack of conductive tiers; a lateral side surface; and a stair step structure including contact regions of at least some of the conductive tiers of the vertical stack of conductive tiers, the stair step structure recessed from the lateral side surface of the three-dimensional memory array block, wherein a portion of the vertical stack of conductive tiers laterally adjacent the stair step structure is free of a stair step structure. - View Dependent Claims (13, 14, 15)
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16. A semiconductor device comprising a memory array block, the memory array block comprising a stack of continuous conductive tiers and a stair step structure between first and second portions of the memory array block, wherein the stair step structure comprises contact regions for respective conductive tiers of the stack of continuous conductive tiers, and wherein:
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the first portion of the memory array block comprises a first plurality of select gates, wherein each select gate of the first plurality of select gates extends in a particular direction over the stack of continuous conductive tiers; and the second portion of the memory array block comprises a second plurality of select gates, wherein each select gate of the second plurality of select gates also extends in the particular direction over the stack of continuous conductive tiers. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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Specification