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Semiconductor device, TFT, capacitor and method of manufacturing the same

  • US 9,165,947 B2
  • Filed: 03/23/2012
  • Issued: 10/20/2015
  • Est. Priority Date: 12/02/2011
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a gate and a first electrode, located on a substrate;

    a first insulating layer, covering the gate and the first electrode;

    an active layer and an etching stop layer, disposed on the first insulating layer above the gate and the first electrode respectively;

    a second insulating layer, covering the active layer and the etching stop layer, wherein the second insulating layer has a first opening, a second opening and a third opening, the first opening and the second opening expose the active layer, and the third opening exposes the etching stop layer and is located above the first electrode;

    a source and a drain, disposed on the second insulating layer and contacting with the active layer through the first opening and the second opening respectively;

    a second electrode, located on the second insulating layer and contacting with the etching stop layer through the third opening, wherein the active layer is between the gate and the source and the drain, and the etching stop layer is disposed between the second electrode and the first electrode; and

    a protecting auxiliary layer, comprising a first protecting pattern layer located on the active layer and a second protecting pattern layer located on the etching stop layer, wherein the first opening and the second opening pass through the first protecting pattern layer, and the third opening passes through the second protecting pattern layer, such that the first protecting pattern layer contacts with the source and the drain, and the second protecting pattern layer contacts with the second electrode, and wherein each of side-walls of the first protecting pattern layer is respectively aligned with one of side-walls of the active layer, and each of side-walls of the second protecting pattern layer is respectively aligned with one of side-walls of the etching stop layer, and wherein the protecting auxiliary layer and the second insulating layer have different patterns.

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