Semiconductor device, TFT, capacitor and method of manufacturing the same

• US 9,165,947 B2
• Filed: 03/23/2012
• Issued: 10/20/2015
• Est. Priority Date: 12/02/2011
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Yan, Jing-Yi, Hsu, Chih-Chieh, Yao, Hsiao-Chiang, Hung, Chu-Yin
• Primary Examiner(s): Nguyen, Khiem D
• Assistant Examiner(s): Vu, Pauline
• Application Number:
  US13/427,904
• Publication Number:
  US 20130140635A1
• Time in Patent Office: 1,306 Days
• Field of Search: 257/43, 257/59, 257/72, 438/149, 438/158
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.

Claims

1. A semiconductor device, comprising:

a gate and a first electrode, located on a substrate;

a first insulating layer, covering the gate and the first electrode;

an active layer and an etching stop layer, disposed on the first insulating layer above the gate and the first electrode respectively;

a second insulating layer, covering the active layer and the etching stop layer, wherein the second insulating layer has a first opening, a second opening and a third opening, the first opening and the second opening expose the active layer, and the third opening exposes the etching stop layer and is located above the first electrode;

a source and a drain, disposed on the second insulating layer and contacting with the active layer through the first opening and the second opening respectively;

a second electrode, located on the second insulating layer and contacting with the etching stop layer through the third opening, wherein the active layer is between the gate and the source and the drain, and the etching stop layer is disposed between the second electrode and the first electrode; and

a protecting auxiliary layer, comprising a first protecting pattern layer located on the active layer and a second protecting pattern layer located on the etching stop layer, wherein the first opening and the second opening pass through the first protecting pattern layer, and the third opening passes through the second protecting pattern layer, such that the first protecting pattern layer contacts with the source and the drain, and the second protecting pattern layer contacts with the second electrode, and wherein each of side-walls of the first protecting pattern layer is respectively aligned with one of side-walls of the active layer, and each of side-walls of the second protecting pattern layer is respectively aligned with one of side-walls of the etching stop layer, and wherein the protecting auxiliary layer and the second insulating layer have different patterns.

2. The semiconductor device as claimed in claim 1, wherein a material of the active layer is the same to a material of the etching stop layer.