Thin film transistor array substrate and liquid crystal display device

• US 9,165,948 B2
• Filed: 10/24/2012
• Issued: 10/20/2015
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Iyama, Yuichi, Yoshioka, Takatomo, Tsuda, Kazuhiko
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US14/351,998
• Publication Number:
  US 20140264330A1
• Time in Patent Office: 1,091 Days
• Field of Search: 257/72
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

The present invention provides a thin film transistor array substrate and a liquid crystal display device including the thin film transistor array substrate that are preferably applicable to a liquid crystal display device including the three-layered electrode structure that enables high response speed and high transmittance, and can have a high aperture ratio. The thin film transistor array substrate of the present invention includes: a thin film transistor element, gate bus lines, and source bus lines, in which the thin film transistor array substrate includes electrodes, the electrodes include a first electrode and a second electrode, the first electrode includes a linear portion along the source bus lines, the first electrode includes a linear portion along the gate bus lines, at least one linear portion along the source bus lines is disposed transversely to the linear portion along the gate bus lines in a plan view of main face of the substrate and is connected to a drain electrode of the thin film transistor element at a position overlapping the gate bus lines, and the second electrode is a planar electrode.

Claims

1. A thin film transistor array substrate, comprising:

a thin film transistor element;

gate bus lines; and

source bus lines,

wherein the thin film transistor array substrate includes a first electrode and a second electrode,

the first electrode includes a linear portion along the source bus lines,

the first electrode includes a linear portion along the gate bus lines,

at least one linear portion along the source bus lines is disposed transversely to the linear portion along the gate bus lines in a plan view of a main face of the substrate and is connected to a drain electrode of the thin film transistor element at a position overlapping the gate bus lines,

the source bus lines include at least two source bus lines that simultaneously drive at least two pixels along the source bus lines, and

the second electrode is a planar electrode.

2. The thin film transistor array substrate according to claim 1,

wherein the linear portion along the source bus lines is longer than the linear portion along the gate bus lines in a plan view of the main face of the substrate.

3. The thin film transistor array substrate according to claim 1,

wherein the first electrode is disposed in each pixel,

the linear portion along the gate bus lines passes through the center of the pixel, and

the first electrodes that are disposed in two pixels adjacent each other along the source bus lines include a structure which is mutually inverted in a plan view of the main face of the substrate.

4. The thin film transistor array substrate according to claim 1,

wherein the first electrode is a pair of comb-shaped electrodes,

one of the pair of comb-shaped electrodes includes a linear portion along the source bus lines, and

the other of the pair of comb-shaped electrodes includes a linear portion along the gate bus lines.

5. The thin film transistor array substrate according to claim 4,

wherein the thin film transistor array substrate includes at least four source bus lines overlapped with one pixel, and

each of two source bus lines disposed inward by one line from outside portions of the pixel is electrically connected to the one of the pair of comb-shaped electrodes or electrically connected to the other of the pair of comb-shaped electrodes.

6. The thin film transistor array substrate according to claim 4,

wherein the thin film transistor array substrate includes at least four source bus lines overlapped with one pixel, and

two source bus lines disposed inward by one line from outside portions of the pixel are connected to outside linear portions of the pair of comb-shaped electrodes.

7. The thin film transistor array substrate according to claim 1,

wherein the planar electrode is commonly connected between pixels in a direction of the source bus lines or pixels in a direction of the gate bus lines.

8. The thin film transistor array substrate according to claim 1,

wherein the thin film transistor element includes an oxide semiconductor.

9. The thin film transistor array substrate according to claim 1,

wherein the first electrode is an electrode for generating a transverse electric field.

10. A liquid crystal display device, comprising the thin film transistor array substrate according to claim 1.