Semiconductor device and method of manufacturing the same

• US 9,166,019 B2
• Filed: 01/09/2014
• Issued: 10/20/2015
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko, Isobe, Atsuo, Hanaoka, Kazuya, Koezuka, Junichi, Sasagawa, Shinya, Kurata, Motomu, Ishizuka, Akihiro
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US14/151,036
• Publication Number:
  US 20140127868A1
• Time in Patent Office: 649 Days
• Field of Search: 257/43, 257/E29.296, 438/104, 438/151, 438/161
• US Class Current: 1/1
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a first electrode layer and a second electrode layer;

forming an oxide semiconductor layer over the first electrode layer and the second electrode layer;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer and a first insulating layer over the gate insulating layer to overlap with the oxide semiconductor layer;

introducing an impurity element into the oxide semiconductor layer using the gate electrode layer and the first insulating layer as masks so that a first region, a second region and a channel formation region between the first region and the second region are formed;

forming a second insulating layer over the first insulating layer to cover side surfaces of the gate electrode layer;

forming a conductive film over the oxide semiconductor layer, the gate electrode layer, the second insulating layer, and the first insulating layer;

forming a first insulating film over the conductive film;

forming a source electrode layer, a drain electrode layer, and a third insulating layer by removing parts of the first insulating film and the conductive film by a chemical mechanical polishing method until the first insulating layer is exposed so that the conductive film is divided; and

forming a fourth insulating layer over the first insulating layer, the second insulating layer, the source electrode layer, the drain electrode layer, and the third insulating layer.

2. The method according to claim 1, wherein the third insulating layer comprises an aluminum oxide layer in contact with the source electrode layer and the drain electrode layer.

3. The method according to claim 1, wherein a resistance of the first region and a resistance of the second region are lower than a resistance of the channel formation region.

4. The method according to claim 1, wherein the fourth insulating layer comprises at least one of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon nitride, aluminum nitride, silicon nitride oxide, and aluminum nitride oxide.

5. The method according to claim 1, wherein the impurity element comprises phosphorus, and wherein an acceleration voltage for introducing the impurity element is 0.5 kV to 80 kV.

6. The method according to claim 1 further comprising:

forming a first wiring layer electrically connected to the first region through a first opening and a second wiring layer electrically connected to the second region through a second opening, wherein the first opening and the second opening are formed in the third insulating layer and the fourth insulating layer,

wherein the first wiring layer overlaps with the first electrode layer, and

wherein the second wiring layer overlaps with the second electrode layer.

7. The method according to claim 6,

wherein the first wiring layer is electrically connected to the first region through the source electrode layer, and

wherein the second wiring layer is electrically connected to the second region through the drain electrode layer.

8. The method according to claim 1, wherein the impurity element is one selected from the group consisting of phosphorus, boron, nitrogen, arsenic, argon, and aluminum.

9. The method according to claim 8, wherein a dosage of the impurity element is 1×

10¹³ ions/cm² to 5×

10¹⁶ ions/cm².

10. A method for manufacturing a semiconductor device comprising the steps of:

forming a first electrode layer and a second electrode layer;

forming an oxide semiconductor layer over the first electrode layer and the second electrode layer;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer over the gate insulating layer to overlap with the oxide semiconductor layer;

introducing an impurity element into the oxide semiconductor layer using the gate electrode layer as a mask so that a first region, a second region and a channel formation region between the first region and the second region are formed;

forming a first insulating layer over the gate electrode layer to cover side surfaces of the gate electrode layer;

forming a source electrode layer over a part of the first region and on a side surface of the first insulating layer, and a drain electrode layer over a part of the second region and on another side surface of the first insulating layer;

forming a second insulating layer over the first insulating layer, the source electrode layer, and the drain electrode layer; and

forming a first wiring layer electrically connected to the first region through a first opening and a second wiring layer electrically connected to the second region through a second opening, wherein the first opening and the second opening are formed in the second insulating laver,

wherein the first wiring layer overlaps with the first electrode layer, and

wherein the second wiring layer overlaps with the second electrode layer.

11. The method according to claim 10,

wherein the first wiring layer is electrically connected to the first region through the source electrode layer, and

wherein the second wiring layer is electrically connected to the second region through the drain electrode layer.

12. The method according to claim 10, wherein a resistance of the first region and a resistance of the second region are lower than a resistance of the channel formation region.

13. The method according to claim 10, wherein the second insulating layer comprises at least one of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon nitride, aluminum nitride, silicon nitride oxide, and aluminum nitride oxide.

14. The method according to claim 10, wherein the impurity element comprises phosphorus, and wherein an acceleration voltage for introducing the impurity element is 0.5 kV to 80 kV.

15. The method according to claim 10, wherein the impurity element is one selected from the group consisting of phosphorus, boron, nitrogen, arsenic, argon, and aluminum.

16. The method according to claim 15, wherein a dosage of the impurity element is 1×

10¹³ ions/cm² to 5×

10¹⁶ ions/cm².

17. A method for manufacturing a semiconductor device comprising the steps of:

forming a first electrode layer and a second electrode layer;

forming an oxide semiconductor layer over the first electrode layer and the second electrode layer;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer and a first insulating layer over the gate insulating layer to overlap with the oxide semiconductor layer;

forming a second insulating layer over the first insulating layer to cover side surfaces of the gate electrode layer;

forming a conductive film over the oxide semiconductor layer, the gate electrode layer, the second insulating layer, and the first insulating layer;

forming a first insulating film over the conductive film;

forming a source electrode layer, a drain electrode layer, and a third insulating layer by removing parts of the first insulating film and the conductive film by a chemical mechanical polishing method until the first insulating layer is exposed so that the conductive film is divided; and

forming a fourth insulating layer over the first insulating layer, the second insulating layer, the source electrode layer, the drain electrode layer, and the third insulating layer.

18. The method according to claim 17, wherein the third insulating layer comprises an aluminum oxide layer in contact with the source electrode layer and the drain electrode layer.

19. The method according to claim 17 further comprising:

forming a first wiring layer electrically connected to the oxide semiconductor layer through a first opening and a second wiring layer electrically connected to the oxide semiconductor layer through a second opening, wherein the first opening and the second opening are formed in the third insulating layer and the fourth insulating layer,

wherein the first wiring layer overlaps with the first electrode layer, and

wherein the second wiring layer overlaps with the second electrode layer.

20. The method according to claim 17, wherein the fourth insulating layer comprises at least one of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon nitride, aluminum nitride, silicon nitride oxide, and aluminum nitride oxide.