Semiconductor device and method for manufacturing the same

• US 9,166,021 B2
• Filed: 10/07/2013
• Issued: 10/20/2015
• Est. Priority Date: 10/17/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tezuka, Sachiaki, Tanaka, Tetsuhiro, Takeuchi, Toshihiko, Suzawa, Hideomi, Hondo, Suguru
• Primary Examiner(s): AU, BAC H
• Application Number:
  US14/047,639
• Publication Number:
  US 20140106502A1
• Time in Patent Office: 743 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide stack over a substrate;

forming a first insulating layer comprising oxygen over the oxide stack; and

forming a gate electrode over the first insulating layer,

wherein the oxide stack comprises;

a first oxide layer comprising indium over the substrate;

an oxide semiconductor layer comprising indium over the first oxide layer; and

a second oxide layer comprising indium over the oxide semiconductor layer,

wherein the first insulating layer is formed under a pressure higher than or equal to 100 Pa and lower than or equal to 300 Pa.

2. The method according to claim 1, wherein the oxide semiconductor layer has a spin density of 1.5×

10¹⁸ spins/cm³ or less.

3. The method according to claim 1, wherein the first insulating layer has a spin density of 2×

10¹⁸ spins/cm³ or more.

4. The method according to claim 1, wherein the first insulating layer is a silicon oxynitride layer.

5. The method according to claim 1, wherein at least any one of the first oxide layer, the oxide semiconductor layer, and the second oxide layer comprises gallium.

6. The method according to claim 1, wherein at least any one of the first oxide layer, the oxide semiconductor layer, and the second oxide layer comprises zinc.

7. The method according to claim 1, wherein the first insulating layer is formed by a plasma CVD method.

8. The method according to claim 1, further comprising the step of forming a source electrode and a drain electrode over the second oxide layer, wherein the first insulating layer is formed over the source electrode and the drain electrode.

9. The method according to claim 1, wherein a difference in electron affinity between the oxide semiconductor layer and at least any one of the first oxide layer and the second oxide layer is greater than or equal to 0.1 eV.

10. The method according to claim 1, further comprising the step of forming a second insulating layer over the substrate,

wherein the first oxide layer is formed over the second insulating layer, and

wherein oxygen is added into the second insulating layer after the second insulating layer is formed.

11. The method according to claim 1, further comprising the step of performing heat treatment at a temperature higher than or equal to 300°

C. and lower than 450°

C. after the first insulating layer is formed.

12. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide stack over a substrate;

forming a first insulating layer comprising oxygen over the oxide stack; and

forming a gate electrode over the first insulating layer,

wherein the oxide stack comprises;

a first oxide layer comprising indium over the substrate;

an oxide semiconductor layer comprising indium over the first oxide layer; and

a second oxide layer comprising indium over the oxide semiconductor layer,

wherein the first insulating layer is formed under a pressure higher than or equal to 100 Pa and lower than or equal to 300 Pa, and

wherein an electron affinity of the oxide semiconductor layer is larger than that of the first oxide layer and that of the second oxide layer.

13. The method according to claim 12, wherein the oxide semiconductor layer has a spin density of 1.5×

10¹⁸ spins/cm³ or less.

14. The method according to claim 12, wherein the first insulating layer has a spin density of 2×

10¹⁸ spins/cm³ or more.

15. The method according to claim 12, wherein the first insulating layer is a silicon oxynitride layer.

16. The method according to claim 12, wherein at least any one of the first oxide layer, the oxide semiconductor layer, and the second oxide layer comprises gallium.

17. The method according to claim 12, wherein at least any one of the first oxide layer, the oxide semiconductor layer, and the second oxide layer comprises zinc.

18. The method according to claim 12, wherein the first insulating layer is formed by a plasma CVD method.

19. The method according to claim 12, further comprising the step of forming a source electrode and a drain electrode over the second oxide layer, wherein the first insulating layer is formed over the source electrode and the drain electrode.

20. The method according to claim 12, wherein a difference in electron affinity between the oxide semiconductor layer and at least any one of the first oxide layer and the second oxide layer is greater than or equal to 0.1 eV.

21. The method according to claim 12, further comprising the step of forming a second insulating layer over the substrate,

wherein the first oxide layer is formed over the second insulating layer, and

wherein oxygen is added into the second insulating layer after the second insulating layer is formed.

22. The method according to claim 12, further comprising the step of performing heat treatment at a temperature higher than or equal to 300°

C. and lower than 450°

C. after the first insulating layer is formed.