Semiconductor device and method for manufacturing the same

• US 9,166,055 B2
• Filed: 06/13/2012
• Issued: 10/20/2015
• Est. Priority Date: 06/17/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Honda, Tatsuya
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US13/495,297
• Publication Number:
  US 20120319114A1
• Time in Patent Office: 1,224 Days
• Field of Search: 257/43
• US Class Current: 1/1
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use, and a semiconductor device including the transistor are provided. In a transistor in which a semiconductor layer, a source electrode layer and a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order over an oxide insulating film, an oxide semiconductor stack composed of at least two oxide semiconductor layers having different energy gaps is used as the semiconductor layer. Oxygen and/or a dopant may be introduced into the oxide semiconductor stack.

Claims

1. A semiconductor device comprising:

an oxide semiconductor stack comprising a first oxide semiconductor layer and a second oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor stack;

an insulating film over the oxide semiconductor stack; and

a gate electrode layer over the insulating film, the gate electrode layer overlapping with the oxide semiconductor stack,

wherein energy gaps of the first oxide semiconductor layer and the second oxide semiconductor layer are different from each other,

wherein the oxide semiconductor stack includes a first region, a second region, a third region, a fourth region, and a fifth region,

wherein the gate electrode layer overlaps the first region,

wherein the source electrode layer is in contact with the second region,

wherein the drain electrode layer is in contact with the third region,

wherein the fourth region and the fifth region are not overlapped by any of the gate electrode layer, the source electrode layer, and the drain electrode layer,

wherein an impurity concentration of the fourth region is higher than that of the second region, and

wherein an impurity concentration of the fifth region is higher than that of the third region.

2. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer is in contact with the insulating film.

3. The semiconductor device according to claim 1, wherein the first region is a channel formation region.

12. The semiconductor device according to claim 1,

wherein an energy gap of the first oxide semiconductor layer is smaller than 3.0 eV, and

wherein an energy gap of the second oxide semiconductor layer is larger than 3.0 eV.

4. A semiconductor device comprising:

an oxide semiconductor stack comprising a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor stack;

an insulating film over the source electrode layer and the drain electrode layer; and

a gate electrode layer over the insulating film, the gate electrode layer overlapping with the oxide semiconductor stack,

wherein the second oxide semiconductor layer is interposed between the first oxide semiconductor layer and the third oxide semiconductor layer, and

wherein an energy gap of the second oxide semiconductor layer is smaller than energy gaps of the first oxide semiconductor layer and the third oxide semiconductor layer.

5. The semiconductor device according to claim 4, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are in contact with the source electrode layer and the drain electrode layer.

6. The semiconductor device according to claim 4, wherein the third oxide semiconductor layer is in contact with the insulating film.

7. The semiconductor device according to claim 4,

wherein the oxide semiconductor stack includes a first region, a second region, a third region, a fourth region, and a fifth region,

wherein the gate electrode layer overlaps the first region,

wherein the source electrode layer overlaps the second region,

wherein the drain electrode layer overlaps the third region,

wherein the fourth region and the fifth region are not overlapped by any of the gate electrode layer, the source electrode layer, and the drain electrode layer.

8. The semiconductor device according to claim 7, wherein the first region is a channel formation region.

9. The semiconductor device according to claim 7,

wherein an impurity concentration of the fourth region is higher than that of the second region, and

wherein an impurity concentration of the fifth region is higher than that of the third region.

10. The semiconductor device according to claim 4,

wherein the energy gaps of the first oxide semiconductor layer and the third oxide semiconductor layer are substantially the same.

11. The semiconductor device according to claim 4, wherein an electron affinity of the second oxide semiconductor layer is higher than electron affinities of the first oxide semiconductor layer and the third oxide semiconductor layer.

13. The semiconductor device according to claim 4,

wherein the energy gaps of the first oxide semiconductor layer and the third oxide semiconductor layer are larger than 3.0 eV, and

wherein the energy gap of the second oxide semiconductor layer is smaller than 3.0 eV.

14. A semiconductor device comprising:

an oxide semiconductor stack comprising a first oxide semiconductor layer and a second oxide semiconductor layer;

a first wiring and a second wiring electrically connected to the oxide semiconductor stack;

an insulating film over the oxide semiconductor stack; and

a gate electrode layer over the oxide semiconductor stack with the insulating film therebetween,

wherein energy gaps of the first oxide semiconductor layer and the second oxide semiconductor layer are different from each other,

wherein the oxide semiconductor stack includes a first region, a second region, a third region, a fourth region, and a fifth region,

wherein the gate electrode layer overlaps the first region,

wherein the first wiring is in contact with the second region,

wherein the second wiring is in contact with the third region,

wherein the fourth region and the fifth region are not overlapped by any of the gate electrode layer, the first wiring, and the second wiring,

wherein an impurity concentration of the fourth region is higher than that of the second region, and

wherein an impurity concentration of the fifth region is higher than that of the third region.

15. The semiconductor device according to claim 14, wherein the first region is a channel formation region.

16. The semiconductor device according to claim 14,

wherein an energy gap of the first oxide semiconductor layer is smaller than 3.0 eV, and

wherein an energy gap of the second oxide semiconductor layer is larger than 3.0 eV.