MTJ stack and bottom electrode patterning process with ion beam etching using a single mask
First Claim
1. A method of fabricating an array of memory pillars on a wafer using a single mask, the method comprising:
- depositing a stack of layers for the array of memory pillars including a top electrode layer and a bottom electrode layer with magnetic tunnel junction (MTJ) layers interposed therebetween, the MTJ layers further comprising a top magnetic layer and a bottom magnetic layer with a barrier layer interposed therebetween;
executing a first etching process to remove areas of at least the top electrode layer and the top magnetic layer not covered by a mask that defines the array of memory pillars; and
performing a second etching process using ion beam etching to remove areas of remaining layers not covered by the mask, including the bottom electrode layer, to form the array of memory pillars while rotating the wafer and to clean exposed sidewalls of the array of memory pillars including sidewalls of patterned bottom electrode layer, and wherein at least a portion of the ion beam etching is performed at a selected ion beam incidence angle greater than zero degree.
7 Assignments
0 Petitions
Accused Products
Abstract
Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.
56 Citations
14 Claims
-
1. A method of fabricating an array of memory pillars on a wafer using a single mask, the method comprising:
-
depositing a stack of layers for the array of memory pillars including a top electrode layer and a bottom electrode layer with magnetic tunnel junction (MTJ) layers interposed therebetween, the MTJ layers further comprising a top magnetic layer and a bottom magnetic layer with a barrier layer interposed therebetween; executing a first etching process to remove areas of at least the top electrode layer and the top magnetic layer not covered by a mask that defines the array of memory pillars; and performing a second etching process using ion beam etching to remove areas of remaining layers not covered by the mask, including the bottom electrode layer, to form the array of memory pillars while rotating the wafer and to clean exposed sidewalls of the array of memory pillars including sidewalls of patterned bottom electrode layer, and wherein at least a portion of the ion beam etching is performed at a selected ion beam incidence angle greater than zero degree. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method of fabricating an array of memory pillars on a wafer using a single mask, the method comprising:
-
depositing a stack of layers for the array of memory pillars including a top electrode layer and a bottom electrode layer with magnetic tunnel junction (MTJ) layers interposed therebetween, the MTJ layers further comprising a top magnetic layer and a bottom magnetic layer with a barrier layer interposed therebetween; forming a mask on top of the top electrode layer for defining the array of memory pillars; executing a first etching process to remove areas of at least the top electrode layer and the top magnetic layer not covered by the mask; and performing a second etching process using ion beam etching to remove areas of remaining layers not covered by the mask, including the bottom electrode layer, to form the array of memory pillars while rotating the wafer and to clean exposed sidewalls of the array of memory pillars including sidewalls of patterned bottom electrode layer, and wherein at least a portion of the ion beam etching is performed at a selected ion beam incidence angle greater than zero degree.
-
Specification