Transceiver

• US 9,166,602 B2
• Filed: 03/24/2010
• Issued: 10/20/2015
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Qorvo International Pte. Ltd. (Qorvo, Inc.)
• Original Assignee: GreenPeak Technologies BV
• Inventors: Van Driest, Hans
• Primary Examiner(s): Urban, Edward
• Assistant Examiner(s): Justus, Ralph H
• Application Number:
  US13/636,350
• Publication Number:
  US 20130005276A1
• Time in Patent Office: 2,036 Days
• Field of Search: 455/76, 455/165.1, 455/183.1, 455/260, 331/16, 331/1
• US Class Current: 1/1
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

A transceiver 1 includes a frequency synthesizer 2 configured to generate an output signal 3 for use as a carrier signal for transmission and/or a signal with a channel frequency for reception, wherein the frequency synthesizer is a sub-sampling based frequency locked loop frequency synthesizer. The combination of a FLL and sub-sampling allows to obtain a sub-sample based locked loop with a closed loop response similar to a PLL but with improved settling time and improved suppression of high frequency components of the quantization noise due to the sampling process. The transceiver allows to obtain a frequency synthesizer with improved characteristics with respect to at least one of power consumption, locking characteristic, design optimization characteristics compared to non-sub-sampling PLL based frequency synthesizers.

Claims

1. A transceiver comprising a frequency synthesizer configured to generate an output signal for use as a carrier signal for transmission and/or a signal with the channel frequency for reception, characterized in that, the frequency synthesizer is a sub-sampling based frequency locked loop frequency synthesizer at which the frequency synthesizer output signal with a frequency f_out is directly sampled with sampling frequency f_sampling wherein f_sampling<

<

f_out,

wherein the frequency locked loop frequency synthesizer comprises;

a frequency detector unit configured to receive a reference frequency signal f_ref and a variable frequency signal and to generate a frequency difference output signal, the difference output signal being a function of a difference between a frequency value associated with the reference frequency signal f_ref and a frequency value associated with the variable frequency signal;

a digital-to-analog convertor configured to convert the frequency difference output signal into an analog frequency difference signal;

a loop filter unit configured to receive the analog frequency difference output signal and configured to attenuate any signal component above a predetermined frequency to provide a smoothed control signal;

a voltage controlled oscillator unit configured to receive the smoothed control signal and to produce an output signal which frequency is a function of the smoothed control signal; and

a sampling unit configured to under-sample the output signal with a predetermined sampling frequency f_sampling to obtain the variable frequency signal that is applied to the frequency detector unit, wherein the variable frequency signal is a P-bit digital signal, P being a positive integer smaller than 8.

2. The transceiver of claim 1, wherein P=1.

3. The transceiver of claim 1, wherein the reference frequency signal f_ref is an adjustable constant M-bit value, wherein the constant M-bit value determines the average frequency of the output signal of the frequency synthesizer, and wherein the frequency detector unit comprises:

a frequency conversion unit configured to convert the variable frequency signal into a digital signal which value represents the frequency of the variable frequency signal and

a signal combination unit configured to combine the reference frequency signal f_ref and the digital signal to obtain the frequency difference signal.

4. The transceiver of claim 3, wherein the frequency conversion unit is configured to generate for each zero-crossing in the variable frequency signal a pulse with a fixed length.

5. The transceiver of claim 1, wherein the reference frequency signal is an adjustable constant M-bit value, wherein the constant M-bit value determines the average frequency of the output signal of the frequency synthesizer, and wherein the frequency detector unit comprises:

a frequency conversion unit configured to convert the variable frequency signal into a digital signal with an average value that represents the frequency of the variable frequency signal;

a signal combination unit configured to combine the reference frequency signal f_ref and the digital signal to obtain an intermediate frequency difference signal; and

a low frequency gain unit configured to receive the intermediate frequency difference signal and to amplify signal components below of a predetermined frequency to obtain the frequency difference output signal.

6. The transceiver of claim 5, wherein the low frequency gain unit comprises

an input to receive the intermediate frequency difference signal;

an integrator unit to perform an integrator function on the intermediate difference signal and to provide an integrated signal;

a multiplication unit configured to multiply the integrated signal with a predetermined value to obtain a multiplied signal;

a signal combination unit configured to combine intermediate frequency difference signal and the multiplied signal to obtain the frequency difference output signal.

7. The transceiver of claim 6, wherein the transceiver further comprises a control unit configured to generate a mode control signal to instruct the low frequency gain unit to switch between a first mode and a second mode, in the first mode the low frequency gain unit is configured to perform an integration function on the intermediate difference signal and in the second mode the low frequency gain unit is configured to freeze the integration function.

8. The transceiver of claim 7, wherein the control unit is configured to switch the low frequency gain unit to the first mode at a predefined time after the low frequency gain unit have been switched in to the second mode.

9. The transceiver of claim 1, wherein the digital-to-analog convertor is a delta-sigma modulator.

10. The transceiver of claim 1, wherein the transceiver is an IEEE 802.15.4 transceiver.

11. Frequency synthesizer having a frequency locked loop synthesizer wherein the frequency locked loop frequency synthesizer comprises:

a frequency detector unit configured to receive a reference frequency signal f_ref and a variable frequency signal and to generate a frequency difference output signal, the difference output signal being a function of a difference between a frequency value associated with the reference frequency signal f_ref and a frequency value associated with the variable frequency signal;

a digital-to-analog convertor configured to convert the frequency difference output signal into an analog frequency difference signal;

a loop filter unit configured to receive the analog frequency difference output signal and configured to attenuate any signal component above a predetermined frequency to provide a smoothed control signal;

a voltage controlled oscillator unit configured to receive the smoothed control signal and to produce an output signal which frequency is a function of the smoothed control signal; and

a sampling unit configured to under-sample the output signal with a predetermined sampling frequency f_sampling to obtain the variable frequency signal that is applied to the frequency detector unit, wherein the variable frequency signal is a P-bit digital signal, P being a positive integer smaller than 8.

12. The frequency synthesizer of claim 11, wherein P=1.

13. The frequency synthesizer of claim 11, wherein the reference frequency signal f_ref is an adjustable constant M-bit value, wherein the constant M-bit value determines the average frequency of the output signal of the frequency synthesizer, and wherein the frequency detector unit comprises:

a frequency conversion unit configured to convert the variable frequency signal into a digital signal which value represents the frequency of the variable frequency signal and

a signal combination unit configured to combine the reference frequency signal f_ref and the digital signal to obtain the frequency difference signal.

14. The frequency synthesizer of claim 13, wherein the frequency conversion unit is configured to generate for each zero-crossing in the variable frequency signal a pulse with a fixed length.

15. The frequency synthesizer of claim 11, wherein the reference frequency signal is an adjustable constant M-bit value, wherein the constant M-bit value determines the average frequency of the output signal of the frequency synthesizer, and wherein the frequency detector unit comprises:

a frequency conversion unit configured to convert the variable frequency signal into a digital signal with an average value that represents the frequency of the variable frequency signal;

a signal combination unit configured to combine the reference frequency signal f_ref and the digital signal to obtain an intermediate frequency difference signal; and

a low frequency gain unit configured to receive the intermediate frequency difference signal and to amplify signal components below of a predetermined frequency to obtain the frequency difference output signal.

16. The frequency synthesizer of claim 15, wherein the low frequency gain unit comprises

an input to receive the intermediate frequency difference signal;

an integrator unit to perform an integrator function on the intermediate difference signal and to provide an integrated signal;

a multiplication unit configured to multiply the integrated signal with a predetermined value to obtain a multiplied signal;

a signal combination unit configured to combine intermediate frequency difference signal and the multiplied signal to obtain the frequency difference output signal.

17. The frequency synthesizer of claim 16, wherein the frequency synthesizer further comprises a control unit configured to generate a mode control signal to instruct the low frequency gain unit to switch between a first mode and a second mode, in the first mode the low frequency gain unit is configured to perform an integration function on the intermediate difference signal and in the second mode the low frequency gain unit is configured to freeze the integration function.

18. The frequency synthesizer of claim 17, wherein the control unit is configured to switch the low frequency gain unit to the first mode at a predefined time after the low frequency gain unit have been switched in to the second mode.

19. The frequency synthesizer of claim 11, wherein the digital-to-analog convertor is a delta-sigma modulator.