Address mapped repartitioned digital pixel with sub-frame residual accumulation
First Claim
1. A readout circuit for an array of detector elements, said readout circuit comprising:
- an array of pixel cells, each of the pixel cells including;
a storage device configured to accumulate a value in response to radiation impinging on a corresponding detector element;
quantization circuitry configured to compare the accumulated value to a threshold value and generate a quantization event;
a logical output configured to report the quantization event; and
a compensator circuit configured to reduce the accumulated value on the storage device to account for the reported quantization event leaving a residual value on the storage device;
at least one digital memory disposed physically separate from the array of pixel cells, said at least one digital memory comprising a plurality of addressable memory locations;
an address mapping input configured to receive an address mapping signal, said signal specifying an address mapping between said pixel cells and said memory locations at multiple times during a frame integration interval;
residual digitization logic configured to capture, digitize and then clear the residual value on the storage device when triggered; and
a control circuit disposed physically separate from the array of pixel cells, said control circuit including;
a shared quantization event selector configured to identify the pixels for which a quantization event is reported, to associate quantization event digital values with those events;
residual capture logic configured to trigger said residual digitization logic at least twice per frame integration interval for selected pixel cells to produce residual digital values;
an address generator configured to use the address mapping to determine addressed memory locations in the digital memory for the pixel cells multiple times during the frame integration interval;
memory update logic configured to accumulate the quantization event digital values or residual digital values for the pixel cells into existing digital values at the addressed memory locations in the digital memory; and
output logic configured to output digital values accumulated over the frame integration interval from at least some of the memory locations.
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Accused Products
Abstract
The accumulation of registered sub-frame residuals in an address-mapped repartitioned digital pixel matches the intensity resolution (dynamic range) to the spatial resolution of the image. The digital accumulation of pixel quantization events (QEs) is extended to include sub-frame residuals. After all QEs are digitally accumulated, then removed from the analog accumulator, an analog residual value remains. Residual capture logic is configured to trigger residual digitization logic at least twice per frame interval for selected pixels to capture, digitize and then clear the residual value on the storage device. Memory update logic is configured to accumulate the quantization event digital values and residual digital values into existing digital values at the address-mapped memory locations in digital memory. Resolution enhancement is enabled by an address mapping that maps a one-pixel spacing on the detector to two or more pixel spacing in the digital memory.
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Citations
20 Claims
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1. A readout circuit for an array of detector elements, said readout circuit comprising:
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an array of pixel cells, each of the pixel cells including; a storage device configured to accumulate a value in response to radiation impinging on a corresponding detector element; quantization circuitry configured to compare the accumulated value to a threshold value and generate a quantization event; a logical output configured to report the quantization event; and a compensator circuit configured to reduce the accumulated value on the storage device to account for the reported quantization event leaving a residual value on the storage device; at least one digital memory disposed physically separate from the array of pixel cells, said at least one digital memory comprising a plurality of addressable memory locations; an address mapping input configured to receive an address mapping signal, said signal specifying an address mapping between said pixel cells and said memory locations at multiple times during a frame integration interval; residual digitization logic configured to capture, digitize and then clear the residual value on the storage device when triggered; and a control circuit disposed physically separate from the array of pixel cells, said control circuit including; a shared quantization event selector configured to identify the pixels for which a quantization event is reported, to associate quantization event digital values with those events; residual capture logic configured to trigger said residual digitization logic at least twice per frame integration interval for selected pixel cells to produce residual digital values; an address generator configured to use the address mapping to determine addressed memory locations in the digital memory for the pixel cells multiple times during the frame integration interval; memory update logic configured to accumulate the quantization event digital values or residual digital values for the pixel cells into existing digital values at the addressed memory locations in the digital memory; and output logic configured to output digital values accumulated over the frame integration interval from at least some of the memory locations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A readout circuit for an array of detector elements, said readout circuit comprising:
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an array of pixel cells, each pixel cell configured to accumulate a value in response to radiation impinging on a corresponding detector element, to compare the accumulated value to a threshold value and generate a quantization event, to report the quantization event and to reduce the accumulated value on the storage device to account for the reported quantization event leaving a residual value on the storage device; at least one digital memory disposed physically separate from the array of pixel cells, said at least one digital memory comprising a plurality of addressable memory locations; an address mapping input configured to receive an address mapping signal; residual digitization logic configured to capture, digitize and then clear the residual value on the storage device when triggered; and a control circuit disposed physically separate from the array of pixel cells, said control circuit configured to identify the pixels for which a quantization event is reported and to associate quantization event digital values with those events, to trigger said residual digitization logic at least twice per frame integration interval for selected pixel cells to produce residual digital values, to use the address mapping to determine addressed memory locations in the digital memory for the pixel cells multiple times during the frame integration interval, to accumulate the quantization event digital values or residual digital values for the pixel cells into existing digital values at the addressed memory locations in the digital memory and to output digital values accumulated over the frame integration interval from at least some of the memory locations.
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20. A method for read out of an array of detector elements, said method comprising:
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at each of a plurality of pixel cells, accumulating a value in response to radiation impinging on a corresponding detector element, comparing the accumulated value to a threshold value to generate a quantization event, reporting the quantization event and reducing the accumulated value on the storage device to account for the reported quantization event leaving a residual value on the storage device; providing at least one digital memory disposed physically separate from the array of pixel cells, said at least one digital memory comprising a plurality of addressable memory locations; receiving an address mapping signal, said signal specifying an address mapping between said pixel cells and said memory locations at multiple times during a frame integration interval; capturing, digitizing and then clearing the residual value on the storage device when triggered; and at a location physically separate from the array of pixel cells, identifying the pixels for which a quantization event is reported and associating quantization event digital values with those events, triggering the capture, digitization and then clearing of the residual value at least twice per frame integration interval for selected pixel cells to produce residual digital values, using the address mapping to determine addressed memory locations in the digital memory for the pixel cells multiple times during the frame integration interval, accumulating the quantization event digital values or residual digital values for the pixel cells into existing digital values at the addressed memory locations in the digital memory and outputting digital values accumulated over the frame integration interval from at least some of the memory locations.
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Specification