Address mapped repartitioned digital pixel with sub-frame residual accumulation

• US 9,167,180 B1
• Filed: 07/07/2014
• Issued: 10/20/2015
• Est. Priority Date: 10/27/2013
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Williams, Darin S., Denham, Martin S.
• Primary Examiner(s): KHAN, USMAN A
• Application Number:
  US14/324,648
• Time in Patent Office: 470 Days
• Field of Search: 348/230.1, 348/231.1, 348/302, 348/308
• US Class Current: 1/1
• CPC Class Codes: H04N 1/2112 using still video cameras
• CPC Class Codes: H04N 25/20 for transforming only infrared radiation into image signals
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/773 comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20

Abstract

The accumulation of registered sub-frame residuals in an address-mapped repartitioned digital pixel matches the intensity resolution (dynamic range) to the spatial resolution of the image. The digital accumulation of pixel quantization events (QEs) is extended to include sub-frame residuals. After all QEs are digitally accumulated, then removed from the analog accumulator, an analog residual value remains. Residual capture logic is configured to trigger residual digitization logic at least twice per frame interval for selected pixels to capture, digitize and then clear the residual value on the storage device. Memory update logic is configured to accumulate the quantization event digital values and residual digital values into existing digital values at the address-mapped memory locations in digital memory. Resolution enhancement is enabled by an address mapping that maps a one-pixel spacing on the detector to two or more pixel spacing in the digital memory.

Claims

1. A readout circuit for an array of detector elements, said readout circuit comprising:

an array of pixel cells, each of the pixel cells including;

a storage device configured to accumulate a value in response to radiation impinging on a corresponding detector element;

quantization circuitry configured to compare the accumulated value to a threshold value and generate a quantization event;

a logical output configured to report the quantization event; and

a compensator circuit configured to reduce the accumulated value on the storage device to account for the reported quantization event leaving a residual value on the storage device;

at least one digital memory disposed physically separate from the array of pixel cells, said at least one digital memory comprising a plurality of addressable memory locations;

an address mapping input configured to receive an address mapping signal, said signal specifying an address mapping between said pixel cells and said memory locations at multiple times during a frame integration interval;

residual digitization logic configured to capture, digitize and then clear the residual value on the storage device when triggered; and

a control circuit disposed physically separate from the array of pixel cells, said control circuit including;

a shared quantization event selector configured to identify the pixels for which a quantization event is reported, to associate quantization event digital values with those events;

residual capture logic configured to trigger said residual digitization logic at least twice per frame integration interval for selected pixel cells to produce residual digital values;

an address generator configured to use the address mapping to determine addressed memory locations in the digital memory for the pixel cells multiple times during the frame integration interval;

memory update logic configured to accumulate the quantization event digital values or residual digital values for the pixel cells into existing digital values at the addressed memory locations in the digital memory; and

output logic configured to output digital values accumulated over the frame integration interval from at least some of the memory locations.

2. The readout circuit of claim 1, wherein the number of memory locations in the digital memory is at least twice the number of pixel cells in the array, wherein each pixel cell maps to a plurality of said memory locations depending upon a sub-pixel alignment of the address mapping such that the accumulated digital values at the addressed memory locations provide an image of the radiation with a higher spatial resolution than the array of detector elements.

3. The readout circuit of claim 1, where said output logic is configured to output the digital values at said higher spatial resolution.

4. The readout circuit of claim 1, wherein said memory update logic is configured to apply individualized gain compensation to each said residual digital value prior to accumulation of the residual digital values.

5. The readout circuit of claim 1, wherein said frame integration interval comprises multiple sub-frame integration intervals, wherein said digital memory comprises quantization event memory and frame memory, wherein said address generator is configured to generate corresponding addressed memory locations in the quantization memory for pixel cells and corresponding addressed memory locations in the frame memory for locations in the quantization event memory, wherein said memory update logic is configured to accumulate the quantization digital events at the addressed memory locations in the quantization memory over each sub-frame integration interval, read the accumulated digital values at the end of each sub-frame integration interval, and accumulate the read accumulated digital values to the addressed memory locations in the frame memory, wherein the output logic is configured to output digital values from the frame memory.

6. The readout circuit of claim 5, wherein said residual capture logic is configured to trigger said residual digitization logic at the end of each sub-frame integration interval, wherein said address generator is further configured to use the address mapping to determine a sub-frame addressed memory locations in the frame memory, wherein said memory update logic is configured to accumulate the residual values directly into the sub-frame addressed memory locations in the frame memory.

7. The readout circuit of claim 1, wherein said residual digitization logic comprises buffers external to said pixels, logic configured to transfer the residual values on said storage devices to said buffers for multiple pixels in parallel before digitization, and A/D converters configured to digitize the values in said buffers before accumulation.

8. The readout circuit of claim 1, wherein said residual digitization logic is configured to convert the residual value on said storage device to a digital representation within each said pixel.

9. The readout of claim 8, wherein said residual digital representation encodes the residual value in said storage device in the transition time of at least one output bit, and wherein logic outside the pixel is configured to convert the time encoded output bit to the residual digital value.

10. The readout of claim 9, wherein said residual digitization logic is configured to use a same said reference signal path and the quantization circuitry in each said pixel to detect the quantization events and to digitize the residual values by placing a time-ramped reference level on a pixel threshold input to the quantization circuitry during residual digitization.

11. The readout of claim 10, wherein said residual digitization logic is further configured to digitize the residuals values for multiple pixels within a group in parallel, and for one or more groups of pixels in series.

12. The readout circuit of claim 1, wherein said memory update logic is configured to accumulate the quantization event digital values and residual values into the same digital memory.

13. The readout circuit of claim 1, wherein said digital memory includes first and second separate memories, wherein said memory update logic is configured to accumulate the quantization event digital values into said first memory and residual values into said second separate memories, respectively.

14. The readout circuit of claim 13, wherein said output logic is configured to output digital values from said first and second separate memories separately.

15. The readout circuit of claim 13, wherein said output logic is configured to merge the output digital values from the first and second memories.

16. The readout circuit of claim 1, wherein the address mapping signal represents motion of a scene with respect to the array of detector elements such that accumulation of the digital values at the address memory locations in the digital memory causes a point in the scene to map to the same memory location as that point moves across the detector elements over the frame integration interval.

17. The readout of claim 1, wherein said address mapping input is configured to specify said address mapping at multiple times during the frame integration interval by receiving new address mapping inputs.

18. The readout of claim 1, wherein said address mapping input is configured to specify said address mapping at multiple times during a frame integration interval by configuring individual address mapping inputs to specify how the said address mapping changes over time.

19. A readout circuit for an array of detector elements, said readout circuit comprising:

an array of pixel cells, each pixel cell configured to accumulate a value in response to radiation impinging on a corresponding detector element, to compare the accumulated value to a threshold value and generate a quantization event, to report the quantization event and to reduce the accumulated value on the storage device to account for the reported quantization event leaving a residual value on the storage device;

at least one digital memory disposed physically separate from the array of pixel cells, said at least one digital memory comprising a plurality of addressable memory locations;

an address mapping input configured to receive an address mapping signal;

residual digitization logic configured to capture, digitize and then clear the residual value on the storage device when triggered; and

a control circuit disposed physically separate from the array of pixel cells, said control circuit configured to identify the pixels for which a quantization event is reported and to associate quantization event digital values with those events, to trigger said residual digitization logic at least twice per frame integration interval for selected pixel cells to produce residual digital values, to use the address mapping to determine addressed memory locations in the digital memory for the pixel cells multiple times during the frame integration interval, to accumulate the quantization event digital values or residual digital values for the pixel cells into existing digital values at the addressed memory locations in the digital memory and to output digital values accumulated over the frame integration interval from at least some of the memory locations.

20. A method for read out of an array of detector elements, said method comprising:

at each of a plurality of pixel cells, accumulating a value in response to radiation impinging on a corresponding detector element, comparing the accumulated value to a threshold value to generate a quantization event, reporting the quantization event and reducing the accumulated value on the storage device to account for the reported quantization event leaving a residual value on the storage device;

providing at least one digital memory disposed physically separate from the array of pixel cells, said at least one digital memory comprising a plurality of addressable memory locations;

receiving an address mapping signal, said signal specifying an address mapping between said pixel cells and said memory locations at multiple times during a frame integration interval;

capturing, digitizing and then clearing the residual value on the storage device when triggered; and

at a location physically separate from the array of pixel cells, identifying the pixels for which a quantization event is reported and associating quantization event digital values with those events, triggering the capture, digitization and then clearing of the residual value at least twice per frame integration interval for selected pixel cells to produce residual digital values, using the address mapping to determine addressed memory locations in the digital memory for the pixel cells multiple times during the frame integration interval, accumulating the quantization event digital values or residual digital values for the pixel cells into existing digital values at the addressed memory locations in the digital memory and outputting digital values accumulated over the frame integration interval from at least some of the memory locations.