Fully integrated voltage regulator using open loop digital control for optimum power stepping and slew rate

• US 9,170,592 B2
• Filed: 09/05/2012
• Issued: 10/27/2015
• Est. Priority Date: 09/05/2012
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Seymour, Michael, Russell, Daniel J.
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Torres-Rivera, Alex
• Application Number:
  US13/603,993
• Publication Number:
  US 20140062442A1
• Time in Patent Office: 1,147 Days
• Field of Search: 323/241, 323/283, 323/322, 323/268, 323/269, 323/271, 323/272, 363/21.05, 363/21.13, 713/300, 713/310, 713/330, 713/340
• US Class Current: 1/1
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

Methods and systems are disclosed for an integrated voltage regulator with open loop digital control for power stepping. In one aspect, a method for regulating an output voltage includes receiving data indicative of a power setting associated with an identified state of an electrical circuit, the power setting based on a load current demand of the electrical circuit in the identified state, enabling one or more parallel driver segments based on the received data indicative of the power setting. The method further includes sourcing by the enabled one or more parallel driver segments sufficient current to meet the load current demand of the electrical circuit in the identified state while maintaining the output voltage at a predetermined voltage level, and providing the output voltage to the electrical circuit at the predetermined voltage level.

Claims

1. A method for regulating an output voltage, the method comprising:

receiving, from a digital state machine, a digital power setting control signal based on an identified state of an electrical circuit comprising a digital core, the identified state representing a predefined operating condition of the electrical circuit, the digital power setting control signal being generated based on a digital logic state of the digital core, the digital logic state indicating a load current demand of the electrical circuit in the identified state in order to maintain the output voltage to the electrical circuit at a predetermined voltage level;

enabling one or more parallel driver segments based on the digital power setting control signal;

sourcing by the enabled one or more parallel driver segments current to meet the load current demand of the electrical circuit in the identified state while maintaining the output voltage at the predetermined voltage level; and

providing the output voltage to the electrical circuit at the predetermined voltage level.

2. The method of claim 1, wherein the identified state of the electrical circuit is identified based on an associated operating load condition of the electrical circuit.

3. The method of claim 2, wherein a load current demand for the identified state is characterized using a power simulation for the associated operating load condition of the electrical circuit.

4. The method of claim 3, further comprising configuring a voltage regulator to regulate the output voltage;

and wherein the characterization of the load current demand for the identified state is performed prior to the configuring of the voltage regulator.

5. The method of claim 4, wherein each of the one or more parallel driver segments comprises a multiplexer and a transistor.

6. The method of claim 5, wherein a size of the transistor is determined based on the characterized load current demand for the state.

7. The method of claim 1, wherein the one or more parallel driver segments provide digital open loop control of the output voltage.

8. The method of claim 7, wherein analog closed loop control maintains the output voltage at the predetermined voltage level.

9. The method of claim 1, wherein the load current demand is at least partially based on a frequency of operation of the digital core.

10. The method of claim 1, wherein the digital logic state of the digital core includes one of multiple states for cryptographic operations performed by the digital core, and

wherein the multiple states include at least one of:

a first state being a steady-state low power mode for the digital core,

a second state being for cryptographic operations that do not include any multiplicative operations,

a third state being for cryptographic operations that include multiplicative operations performed with a use of a first multiplier, or

a fourth state being for cryptographic operations that include multiplicative operations performed with a use of a second multiplier at a clock rate greater than a clock rate used in the third state.

11. A system comprising:

an electrical circuit comprising a digital core;

a digital state machine configured to identify one or more states of the electrical circuit, wherein each of the one or more identified states is based on a respective power setting, the power setting based on a digital logic state indicating a load current demand of the digital core of the electrical circuit in the identified state in order to maintain an output voltage to the electrical circuit at a predetermined voltage level, the identified state representing a predefined operating condition of the electrical circuit;

one or more parallel driver segments configured to source current in order to meet the load current demand of the electrical circuit in a corresponding identified state of the one or more identified states; and

an amplifier configured to accommodate system load changes for a power range of the power setting associated with the identified state in order to maintain the output voltage at the predetermined voltage level for the identified state.

12. The system of claim 11, wherein the one or more states of the electrical circuit are identified based on one or more respective operating load conditions of the electrical circuit.

13. The system of claim 12, wherein a load current demand for each of the one or more identified states is characterized using power simulations for each respective operating load condition of the electrical circuit.

14. The system of claim 13, further comprising:

a voltage regulator configured to regulate the output voltage, wherein;

the voltage regulator includes the one or more parallel driver segments and the amplifier; and

the characterization of the load current demand for each of the one or more identified states is performed prior to configuring the voltage regulator.

15. The system of claim 11, wherein the one or more parallel driver segments provide digital open loop control of the output voltage.

16. The system of claim 15, wherein one of the one or more parallel driver segments comprises a multiplexer and a transistor.

17. The system of claim 16, wherein a size of the transistor is determined based on the characterized load current demand for a respective identified state.

18. The system of claim 15, wherein analog closed loop control maintains the output voltage at the predetermined voltage level.

19. The system of claim 18, further comprising:

a resistor divider that samples the output voltage; and

wherein maintaining the output voltage at the predetermined voltage level comprises;

comparing, by the amplifier, the sampled output voltage to a reference voltage; and

adjusting the output voltage based on the comparing, by the amplifier, of the sampled output voltage to the reference voltage.

20. The system of claim 11, wherein the digital logic state includes one of multiple states for cryptographic operations performed by the digital core, and

wherein the multiple states include at least one of:

a first state being a steady-state low power mode for the digital core,

a second state being for cryptographic operations that do not include any multiplicative operations,

a third state being for cryptographic operations that include multiplicative operations performed with a use of a first multiplier, or

a fourth state being for cryptographic operations that include multiplicative operations performed with a use of a second multiplier at a clock rate greater than a clock rate used in the third state.