Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system
First Claim
1. An apparatus, comprising:
- a memory system including;
NAND flash physical memory;
RAM physical memory;
a first buffer for receiving DDR signals, over a DDR bus, and converting the DDR signals to SATA signals; and
second buffer for receiving the SATA signals and converting the SATA signals to NAND flash signals, the second buffer communicatively coupled to the first buffer via a first memory bus associated with a SATA protocol, the second buffer further communicatively coupled to the NAND flash physical memory via a second memory bus associated with a NAND flash protocol, the second buffer further communicatively coupled to the RAM physical memory;
said memory system configured for;
receiving, over the DDR bus, a special command and special data that are responsive to a communication from another system,after the receipt of the special command and the special data, processing at least one of the special command or the special data for causing particular data in the NAND flash physical memory to be written to the RAM physical memory, andafter a status in connection with the memory system, receiving a read command to read the particular data written to the RAM physical memory after the receipt of the special command and the special data.
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Accused Products
Abstract
A computer program product, apparatus and associated method/processing unit are provided for utilizing a memory subsystem including NAND flash physical memory and DRAM physical memory. Further included is a first buffer for receiving DDR signals and converting the DDR signals to SATA signals. The first buffer includes embedded DRAM physical memory. Also provided is a second buffer for receiving the SATA signals and converting the SATA signals to NAND flash signals. The second buffer is communicatively coupled to the first buffer via a first memory bus associated with a SATA protocol, the NAND flash physical memory via a second memory bus associated with a NAND flash protocol, and the DRAM physical memory.
488 Citations
20 Claims
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1. An apparatus, comprising:
a memory system including; NAND flash physical memory; RAM physical memory; a first buffer for receiving DDR signals, over a DDR bus, and converting the DDR signals to SATA signals; and second buffer for receiving the SATA signals and converting the SATA signals to NAND flash signals, the second buffer communicatively coupled to the first buffer via a first memory bus associated with a SATA protocol, the second buffer further communicatively coupled to the NAND flash physical memory via a second memory bus associated with a NAND flash protocol, the second buffer further communicatively coupled to the RAM physical memory; said memory system configured for; receiving, over the DDR bus, a special command and special data that are responsive to a communication from another system, after the receipt of the special command and the special data, processing at least one of the special command or the special data for causing particular data in the NAND flash physical memory to be written to the RAM physical memory, and after a status in connection with the memory system, receiving a read command to read the particular data written to the RAM physical memory after the receipt of the special command and the special data. - View Dependent Claims (2)
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3. An apparatus, comprising:
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NAND flash memory; random access memory; a first circuit for receiving DDR signals and converting the DDR signals to SATA signals, the first circuitry for receiving a special command and special data via a DDR bus after a system communication; and a second circuit for receiving the SATA signals and converting the SATA signals to NAND flash signals, the second circuit communicatively coupled to the first circuit via a first memory bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a second memory bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory, the second circuit for, after the special command and the special data, causing information in the NAND flash memory to be written to the random access memory based on a processing of at least one of the special command or the special data, for allowing the information to be read in connection with a read command that is based on a status check after the special command and the special data. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An apparatus, comprising:
a processing unit configured for working in conjunction with a driver to enable a random access data read from a memory sub-system including; NAND flash memory; random access memory; a first circuit for receiving DDR signals and converting the DDR signals to SATA signals; and a second circuit for receiving the SATA signals and converting the SATA signals to NAND flash signals, the second circuit communicatively coupled to the first circuit via a first memory bus capable of utilizing a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a second memory bus capable of utilizing a NAND flash protocol, the second circuit further communicatively coupled to the random access memory, the random access data read enabled by the processing unit, by; enabling transmission, via the driver and over a DDR bus, a special command and special data to the memory sub-system, for causing particular data in the NAND flash memory to be written to the random access memory, and based on a status in connection with the memory sub-system, enabling transmission, via the driver and over the DDR bus, a read command to read the particular data written to the random access memory. - View Dependent Claims (19, 20)
Specification