Method and apparatus for scrubbing accumulated data errors from a memory system

• US 9,170,879 B2
• Filed: 06/24/2009
• Issued: 10/27/2015
• Est. Priority Date: 06/24/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Headway Technologies Incorporated
• Inventors: Yang, Hsu Kai
• Primary Examiner(s): SCHELL, JOSEPH O
• Application Number:
  US12/456,923
• Publication Number:
  US 20100332900A1
• Time in Patent Office: 2,316 Days
• Field of Search: 714/718
• US Class Current: 1/1
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1096 Parity calculation or recalculation after configuration or reconfiguration of the system
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/46 Test trigger logic

Abstract

A data scrubbing apparatus corrects disturb data errors occurring in an array of memory cells such as SMT MRAM cells. The data scrubbing apparatus receives an error indication that an error has occurred during a read operation of a grouping of memory cells within the array of memory cells. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data. Based on a scrub threshold value, the data scrubbing apparatus writes the corrected data back after a specific number of errors. The data scrubbing apparatus may further suspend writing back during a writing of data. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

Claims

1. A data scrubbing apparatus for correcting disturb data errors occurring in an array of SMT MRAM memory cells, the data scrubbing apparatus comprising:

an error flag bus in communication with error correcting circuitry within the array of memory cells configured for providing an error flag signal indicating a number of detectable and correctable errors occurring in data accessed during one data read operation in a grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells;

an error flag detector in communication with error flag bus for receiving the error flag signal and configured for accumulating an error count of detected and corrected errors during one data read operation of the grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells;

an address generator configured for regenerating an original address of the data having the error in the grouping of the SMT MRAM memory cells within the SMT MRAM memory array and error correction code bits covering the grouping of SMT MRAM memory cells; and

a write back control device in communication with the error flag detector to receive the error count and configured for comparing the error count with a received scrub threshold signal that provides a threshold value for the number of errors within the grouping of SMT MRAM memory cells that are to be tolerated before scrubbing the grouping of the array of SMT MRAM memory cells, wherein the scrub threshold value is less than or equal to a maximum number of errors that are detectable and correctable by an error correction/detection circuit and in communication with the address generator to receive the regenerated original address and wherein the write back control device is configured for controlling writing back of data corrected subsequent to the one data read operation to the grouping of the SMT MRAM memory cells.

2. The data scrubbing apparatus of claim 1 further comprising a data multiplexer for receiving provided data to be written to the array of the SMT MRAM memory cells and the corrected data and upon receiving a write back signal from the write back control device, transferring the selected one of the provided data and the corrected data to the array of SMT MRAM memory cells.

3. The data scrubbing apparatus of claim 1 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

4. The data scrubbing apparatus of claim 1 wherein the scrub threshold value indicates that the write back control device issues a write back signal after receipt of the error flag signal, the error flag signal indicative of a number of errors corrected by error correcting circuitry within the array of SMT MRAM memory cells.

5. The data scrubbing apparatus of claim 1 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of SMT MRAM memory cells when a specific number of errors occurs in the grouping of the array of SMT MRAM memory cells.

6. The data scrubbing apparatus of claim 1 wherein the write back control device suspends writing back during a writing of data to the array of SMT MRAM memory cells.

7. The data scrubbing apparatus of claim 1 wherein the write back control device provides a busy indicator externally to the array of SMT MRAM memory cells during a write back of corrected data.

8. The data scrubbing apparatus of claim 1 wherein the error is caused by the one data read operation disturb or any phenomenon that causes a shift the magnetic orientation of the SMT MRAM cells.

9. The data scrubbing apparatus of claim 1 wherein the data scrubbing apparatus is activated at an as needed non-periodic basis.

10. The data scrubbing apparatus of claim 1 further comprising an address multiplexer configured for receiving at least one external address identifying locations within the array of SMT MRAM memory cells to be written to or read from and for receiving the regenerated original address, and connected to the write back control device receiving a write back signal and configured for transferring the selected one of the at least one external address and the regenerated original address to the array of SMT MRAM memory cells.

11. A memory device comprising:

a data scrubbing apparatus for correcting disturb data errors occurring in an array of SMT MRAM memory cells within the memory device, the data scrubbing apparatus comprising;

an error flag bus in communication with error correcting circuitry within the array of SMT MRAM memory cells configured for providing an error flag signal indicating a number of detectable and correctable errors occurring in data accessed during one data read operation in a grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells;

an error flag detector in communication with the error flag bus for receiving the error flag signal configured for accumulating an error count of the detected and corrected errors during the one data read operation of a grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells;

an address generator configured for regenerating an original address of the data having the error in the grouping of the SMT MRAM memory cells within the memory array and error correction code bits covering the grouping of SMT MRAM memory cells; and

a write back control device in communication with the error flag detector to receive the error count and configured for comparing the error count with a received scrub threshold signal that provides a threshold value for the number of errors within the grouping of SMT MRAM memory cells that are to be tolerated before scrubbing the grouping of the array of SMT MRAM memory cells, wherein the scrub threshold value is less than or equal to the maximum number of errors that are detectable and correctable by an error correction/detection circuit and wherein the write back control device is in communication with the address generator to receive the regenerated original address and wherein the write back control device is configured for controlling writing back of data corrected subsequent to the one data read operation to the grouping of the SMT MRAM memory cells.

12. The memory device of claim 11 wherein the data scrubbing apparatus further comprises a data multiplexer for receiving provided data to be written to the array of the SMT MRAM memory cells and the corrected data and upon receiving a write back signal from the address generator transferring the selected one of the provided data and the corrected data to the array of SMT MRAM memory cells.

13. The memory device of claim 11 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

14. The memory device of claim 11 wherein the scrub threshold value indicates that the write back control device issues a write back signal after receipt of the error flag signal indicative of a number of errors corrected by error correcting circuitry within the array of SMT MRAM memory cells.

15. The memory device of claim 11 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of SMT MRAM memory cells when a specific number of errors occurs in the grouping of the array of SMT MRAM memory cells.

16. The memory device of claim 11 wherein the write back control device suspends writing back during a writing of data to the array of SMT MRAM memory cells.

17. The memory device of claim 11 wherein the write back control device provides a busy indicator externally to the array of SMT MRAM memory cells during a write back of corrected data.

18. The memory device of claim 11 wherein the error is caused by the one data read operation disturb or any phenomenon that causes a shift the magnetic orientation of the SMT MRAM cells.

19. The memory device of claim 11 wherein the data scrubbing apparatus is activated at an as needed non-periodic basis.

20. The memory device of claim 11 wherein the data scrubbing apparatus further comprises an address multiplexer configured for receiving at least one external address identifying locations within the array of SMT MRAM memory cells to be written to or read from and for receiving the regenerated original address, and connected to the write back control device receiving a write back signal and configured for transferring the selected one of the at least one external address and the regenerated original address to the array of SMT MRAM memory cells.

21. A method for scrubbing disturb data errors occurring in an array of memory cells comprising the steps of:

receiving an error flag signal indicating a number of detectable and correctable errors occurring during one data read operation in a grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells;

accumulating an error count of detected and corrected errors detected during the one data read operation of the grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells;

receiving a scrub threshold signal that provides a threshold value for the number of errors within the grouping of SMT MRAM memory cells that are to be tolerated before scrubbing the grouping of the SMT MRAM array of memory cells, wherein the threshold value is less than or equal to the maximum number of errors that are detectable and correctable by an error correction/detection circuit;

comparing the accumulated error count with the received scrub threshold signal;

regenerating an original address of the data having the error in the grouping of the SMT MRAM memory cells within the SMT MRAM memory array and error correction code bits covering the grouping of SMT MRAM memory cells when the number of errors in the grouping of SMT MRAM memory cells exceeds a scrub threshold value; and

writing corrected data back to the grouping of SMT MRAM memory cells at the location designated by the regenerated original address of the data having the error.

22. The method for scrubbing disturb data errors of claim 21 further comprising multiplexing provided data to be written to the array of the SMT MRAM memory cells and the corrected data for transferring the selected one of the provided data and the corrected data to the array of SMT MRAM memory cells.

23. The method for scrubbing disturb data errors of claim 21 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

24. The method for scrubbing disturb data errors of claim 21 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of SMT MRAM memory cells when a specific number of errors occurs in the grouping of the array of SMT MRAM memory cells.

25. The method for scrubbing disturb data errors of claim 21 further comprises suspending writing back during a writing of provided data to the array of SMT MRAM memory cells.

26. The method for scrubbing disturb data errors of claim 21 further comprising providing a busy indicator externally to the array of SMT MRAM memory cells during a write back of corrected data.

27. The method for scrubbing disturb data errors of claim 21 wherein the error is caused by the one data read operation disturb or any phenomenon that causes a shift the magnetic orientation of the SMT MRAM cells.

28. The method for scrubbing disturb data errors of claim 21 further comprising activating the method for data scrubbing data errors at an as needed non-periodic basis.

29. The method for scrubbing disturb data errors of claim 21 further comprising the step of multiplexing at least one external address identifying locations within the array of SMT MRAM memory cells to be written to or read from and the regenerated original address based on a state of a write back signal for transferring the selected one of the at least one external address and the regenerated original address to the array of SMT MRAM memory cells.

30. An apparatus for scrubbing disturb data errors occurring in an array of SMT MRAM memory cells comprising:

means for receiving an error flag signal indicating a number of detectable and correctable errors occurring during one data read operation in a grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells;

means for accumulating an error count of detected and corrected errors detected during one data read operation of the grouping of the SMT MRAM memory cells within the array of SMT MRAM memory cells;

means for receiving a scrub threshold signal that provides a threshold value for the number of errors within the grouping of SMT MRAM memory cells that are to be tolerated before scrubbing the grouping of the array of SMT MRAM memory cells, wherein the scrub threshold value is less than or equal to the maximum number of errors that are detectable and correctable by an error correction/detection circuit;

means for comparing the accumulated error count with the received scrub threshold signal;

means for regenerating an original address of the data having the error in the grouping of the SMT MRAM memory cells within the memory array and error correction code bits covering the grouping of SMT MRAM memory cells when the number of errors in the grouping of SMT MRAM memory cells exceeds a scrub threshold value; and

means for writing corrected data back to the grouping of memory cells at the location designated by the regenerated original address of the data having the error.

31. The apparatus for scrubbing disturb data errors of claim 30 further comprising means for multiplexing provided data to be written to the array of the SMT MRAM memory cells and the corrected data for transferring the selected one of the provided data and the corrected data to the array of SMT MRAM memory cells.

32. The apparatus for scrubbing disturb data errors of claim 30 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

33. The apparatus for scrubbing disturb data errors of claim 30 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of SMT MRAM memory cells when a specific number of errors occurs in the grouping of the array of SMT MRAM memory cells.

34. The apparatus for scrubbing disturb data errors of claim 30 further comprises means for suspending writing back during a writing of provided data to the array of SMT MRAM memory cells.

35. The apparatus for scrubbing disturb data errors of claim 30 further comprising means for providing a busy indicator externally to the array of SMT MRAM memory cells during a write back of corrected data.

36. The apparatus for scrubbing disturb data errors of claim claim 30 wherein the error is caused by the one data read operation disturb or any phenomenon that causes a shift the magnetic orientation of the SMT MRAM cells.

37. The apparatus for scrubbing disturb data errors of claim 30 further comprising a means for activating the apparatus for data scrubbing data errors at an as needed non-periodic basis.

38. The apparatus for scrubbing disturb data errors of claim 30 further comprising means for multiplexing at least one external address identifying locations within the array of SMT MRAM memory cells to be written to or read from and the regenerated original address based on a state of a write back signal for transferring the selected one of the at least one external address and the regenerated original address to the array of SMT MRAM memory cells.

39. An MRAM device comprising:

a data scrubbing apparatus for correcting disturb data errors occurring in an array of MRAM cells within the MRAM device, the data scrubbing apparatus comprising;

an error flag bus in communication with error correcting circuitry within the array of memory cells configured for providing an error flag signal indicating a number of detectable and correctable errors occurring in data accessed during one data read operation in a grouping of the MRAM cells within the array of MRAM cells;

an error flag detector in communication with error flag bus for receiving the error flag signal configured for accumulating an error count of the detected and corrected errors during the one data read operation of the grouping of the MRAM cells within the array of MRAM cells;

an address generator configured for regenerating an original address of data having detected and corrected errors in the grouping of the MRAM cells within the array of MRAM cells and error correction code bits covering the grouping of MRAM cells; and

a write back control device in communication with the error flag detector to receive the error count and compare the error count with a received scrub threshold signal that provides a threshold value for the number of errors within the grouping of MRAM cells that are to be tolerated before scrubbing the grouping of the array of MRAM cells, wherein the scrub threshold value is less than or equal to the maximum number of errors that are detectable and correctable by an error correction/detection circuit and wherein the write back control device is in communication with the address generator to receive the regenerated original address and wherein the write back control device is configured for controlling writing back of data corrected subsequent to the one data read operation to the grouping of the MRAM cells.

40. The MRAM device of claim 39 wherein the data scrubbing apparatus further comprises a data multiplexer for receiving provided data to be written to the array of the MRAM cells and the corrected data and upon receiving a write back signal from the address generator transferring a selected one of the provided data and the corrected data to the array of MRAM cells.

41. The MRAM device of claim 39 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

42. The MRAM device of claim 39 wherein the scrub threshold value indicates that the write back control device issues a write back signal after receipt of the error flag signal indicative of a number of errors corrected by error correcting circuitry within the array of MRAM cells.

43. The MRAM device of claim 39 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of MRAM cells.

44. The MRAM device of claim 39 wherein the write back control device suspends writing back during a writing of data to the array of MRAM cells.

45. The MRAM device of claim 39 wherein the write back control device provides a busy indicator externally to the array of MRAM cells during a write back of corrected data.

46. The MRAM device of claim 39 wherein the MRAM cells within the array of MRAM cells are SMT MRAM cells.

47. The MRAM device of claim 39 wherein the error is caused by the one data read operation disturb or any phenomenon that causes a shift the magnetic orientation of the MRAM cells.

48. The MRAM device of claim 39 wherein the data scrubbing apparatus is activated at an as needed non-periodic basis.

49. The MRAM device of claim 39 wherein the data scrubbing apparatus further comprises an address multiplexer configured for receiving at least one external address identifying locations within the array of MRAM cells to be written to or read from and for receiving the regenerated original address, and connected to the write back control device receiving a write back signal and configured for transferring the selected one of the at least one external address and the regenerated original address to the array of MRAM cells.