Method and system for atomically writing scattered information in a solid state storage device

• US 9,170,938 B1
• Filed: 10/22/2013
• Issued: 10/27/2015
• Est. Priority Date: 05/17/2013
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Walsh, James J., Tomlin, Andrew J.
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US14/060,547
• Time in Patent Office: 735 Days
• Field of Search: 710/62, 711/104, 711/154
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery
• CPC Class Codes: G06F 11/1474 in transactions G06F16/20 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.

Claims

1. A method of performing an operation in a data storage device, the method comprising:

receiving an atomic write command;

obtaining a plurality of ranges of logical addresses affected by the atomic write command;

for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range;

performing the write operations in the ranges of logical addresses;

updating the metadata information upon completion of the write operations in the ranges; and

deferring an update to a translation map of the data storage device until the metadata information has been updated.

2. The method of claim 1, wherein each range in the plurality of ranges of logical addresses affected is contiguous.

3. The method of claim 1, wherein the metadata for each range is unique to the write operation performed at the associated range of logical addresses.

4. The method of claim 3, wherein the metadata for each associated write operation comprises:

a sequence number of a plurality of sequence numbers assigned to the write command; and

a slot number.

5. The method of claim 4, further comprising providing a plurality of slots in a power-safe storage, wherein each slot in the plurality of slots that are associated with the atomic write command is configured to store one of the plurality of sequence numbers.

6. The method of claim 5, wherein updating the metadata information upon completion of the write operations in the ranges comprises:

changing, in the power-safe storage, the sequence numbers associated with the atomic write command after all the write operations are completed.

7. The method of claim 6, wherein the changing of the sequence numbers enables reconstruction to determine whether the atomic write command has completed.

8. The method of claim 6, wherein the changing comprises, when a write operation performed at one of the ranges completes, changing the sequence number associated with that range.

9. The method of claim 5, wherein the power-safe storage comprises one of a magnetic random access memory (MRAM), a battery-backed random access memory and a non-volatile random access memory (NVRAM).

10. The method of claim 1, further comprising:

after all the data specified by the atomic write command have been written and the metadata updated, updating the translation map.

11. The method of claim 10, further comprising:

acknowledging a completion of the atomic write command to a host coupled to the data storage device after the translation map has been updated.

12. The method of claim 1, wherein the translation map is configured to store mapping entries spanning at least a portion of a logical capacity of the data storage device and wherein mapping information for the atomic write command includes one or more logical addresses that extend beyond the logical capacity of the data storage device.

13. A controller in a data storage device, the controller comprising:

a processor configured to;

receive an atomic write command;

obtain a plurality of ranges of logical addresses associated with a plurality of non-volatile solid-state memory devices of the data storage device that are affected by the atomic write command;

for each of the plurality of affected ranges, assign metadata information to track completion of a write operation performed at that range;

cause the write operations to be executed in the ranges of logical addresses in the non-volatile solid-state memory devices;

update the metadata information upon completion of the write operations in the ranges; and

defer an update to a translation map of the data storage device until the metadata information has been updated.

14. The controller of claim 13, wherein each range in the plurality of ranges of logical addresses affected is contiguous.

15. The controller of claim 13, wherein the metadata for each range is unique to the write operation performed at the associated range of logical addresses.

16. The controller of claim 15, wherein the metadata for each associated write operation comprises:

a sequence number of a plurality of sequence numbers assigned to the write command; and

a slot number.

17. The controller of claim 16, wherein the controller is further configured to use a plurality of slots in a power-safe storage, wherein each slot in the plurality of slots that are associated with the atomic write command is configured to store one of the plurality of sequence numbers.

18. The controller of claim 17, wherein the controller is further configured to update the metadata information upon completion of the write operations in the ranges by at least:

changing, in the power-safe storage, the sequence numbers associated with the atomic write command after all the write operations are completed.

19. The controller of claim 18, wherein the changing of the sequence numbers enables reconstruction to determine whether the atomic write command has completed.

20. The controller of claim 18, wherein the changing comprises, when a write operation performed at one of the ranges completes, changing the sequence number associated with that range.

21. The controller of claim 17, wherein the power-safe storage comprises one of a magnetic random access memory (MRAM), a battery-backed random access memory and a non-volatile random access memory (NVRAM).

22. The controller of claim 13, wherein the controller is further configured to:

after all the data specified by the atomic write command have been written and the metadata updated, update the translation map.

23. The controller of claim 22, wherein the controller is further configured to:

acknowledge a completion of the atomic write command to a host coupled to the data storage device after the translation map has been updated.

24. The controller of claim 13, wherein the translation map is configured to store mapping entries spanning at least a portion of a logical capacity of the data storage device and wherein mapping information for the atomic write command includes one or more logical addresses that extend beyond the logical capacity of the data storage device.

25. A data storage device comprising:

a plurality of non-volatile solid-state memory devices; and

a controller comprising;

a processor configured to;

receive an atomic write command;

obtain a plurality of ranges of logical addresses associated with the plurality of non-volatile solid-state memory devices of the data storage device that are affected by the atomic write command;

for each of the plurality of affected ranges, assign metadata information to track completion of a write operation performed at that range;

cause the write operations to be executed in the ranges of logical addresses in the non-volatile solid-state memory devices;

update the metadata information upon completion of the write operations in the ranges; and

defer an update to a translation map of the data storage device until the metadata information has been updated.

26. The data storage device of claim 25,

wherein the metadata for each range is unique to the write operation performed at the associated range of logical addresses.

27. The data storage device of claim 26, wherein the metadata for each associated write operation comprises:

a sequence number of a plurality of sequence numbers assigned to the write command; and

a slot number.

28. The data storage device of claim 27, wherein the controller is further configured to use a plurality of slots in a power-safe storage, wherein each slot in the plurality of slots that are associated with the atomic write command is configured to store one of the plurality of sequence numbers.

29. The data storage device of claim 25, wherein the controller is further configured to:

after all the data specified by the atomic write command have been written and the metadata updated, update the translation map.

30. The data storage device of claim 29, wherein the controller is further configured to:

acknowledge a completion of the atomic write command to a host coupled to the data storage device after the translation map has been updated.

31. The data storage device of claim 25, wherein the translation map is configured to store mapping entries spanning at least a portion of a logical capacity of the data storage device and wherein mapping information for the atomic write command includes one or more logical addresses that extend beyond the logical capacity of the data storage device.