Data hardening in a storage system

• US 9,170,941 B2
• Filed: 11/15/2013
• Issued: 10/27/2015
• Est. Priority Date: 04/05/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Ellis, Robert W., Herman, Lace J., Southerland, Bobby Ray
• Primary Examiner(s): Unelus, Ernest
• Assistant Examiner(s): LEWIS-TAYLOR, DAYTON A.
• Application Number:
  US14/081,992
• Publication Number:
  US 20140304454A1
• Time in Patent Office: 711 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/262 configured as RAID
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/311 In host system
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A storage system, and a method of data hardening in the storage system, including: a de-glitch module configured for a detection of a power failure event; a write page module, coupled to the de-glitch module, the write page module configured for an execution of a cache write command based on the power failure event to send a cache page from a cache memory to a storage channel controller, wherein the cache memory is a volatile memory; and a signal empty module, coupled to the write page module, the signal empty module configured for a generation of a sleep signal to shut down a host bus adapter, wherein the host bus adapter interfaces with the storage channel controller to write the cache page back to the cache memory upon a power up of the host bus adapter and the storage channel controller.

Claims

1. A method of data hardening in a storage system comprising:

detecting a power failure event;

executing a cache write command based on the power failure event to send a cache page from a cache memory to nonvolatile memory in the storage system, wherein the cache memory is volatile memory, wherein executing the cache write command includes writing the cache page and meta-data to nonvolatile memory in the storage system using logical block addresses outside a predetermined logical address space, and the predetermined logical address space includes logical addresses allocated for storing data during normal operation of the storage system; and

generating a sleep signal to shut down a host bus adapter, wherein the host bus adapter interfaces with a storage channel controller to write the cache page back to the cache memory upon a power up of the host bus adapter and the storage channel controller.

2. The method as claimed in claim 1, further comprising aborting a read command upon detecting the power failure event.

3. The method as claimed in claim 1, wherein executing the cache write command includes executing the cache write command to write the cache page and the meta-data to fast pages of multi-level cell portions or single level cell portions of nonvolatile memory in the storage device.

4. The method as claimed in claim 1, further comprising generating a controller cache data parity to write to a nonvolatile memory device, wherein the controller cache data parity is for the cache page.

5. The method as claimed in claim 1, wherein executing the cache write command includes executing the cache write command to write scram data to a controller scram memory by the storage channel controller based on the cache page.

6. The method as claimed in claim 1, further comprising:

aborting a read command upon detecting the power failure event; and

aborting a wear leveling operation after aborting the read command.

7. The method as claimed in claim 1, wherein generating the sleep signal to shut down the host bus adapter comprises generating the sleep signal to shut down the host bus adapter after executing the cache write command.

8. The method as claimed in claim 1, further comprising:

starting a timer upon detecting the power failure event, wherein the timer designates a period of time for write commands to send data to the nonvolatile memory in the storage system.

9. A storage system comprising:

a cache memory configured to store a cache page, wherein the cache memory is volatile memory;

a de-glitch module configured to detect a power failure event;

a host bus adapter, coupled to the de-glitch module, wherein the host bus adapter includes;

a write page module, coupled to the de-glitch module, the write page module configured to execute a cache write command based on the detected power failure event, wherein the executed cache write command writes the cache page and meta-data to nonvolatile memory in the storage system using logical block addresses outside a predetermined logical address space, and the predetermined logical address space includes logical addresses allocated for storing data during normal operation of the storage system; and

a signal empty module, coupled to the write page module, the signal empty module configured to generate a sleep signal to shut down the host bus adapter; and

a storage channel controller, coupled to the host bus adapter, the storage channel controller configured to receive the cache page and the meta-data from the cache memory and for an interface with the host bus adapter to write the cache page back to the cache memory upon a power up of the host bus adapter and the storage channel controller.

10. The system as claimed in claim 9, wherein the storage channel controller includes a controller abort read module, coupled to the de-glitch module, the controller abort read module configured to abort a read command based on the detected power failure event.

11. The system as claimed in claim 9, wherein the host bus adapter includes the write page module configured to execute the cache write command to write the cache page and the meta-data to fast pages of multi-level cell portions or single level cell portions of nonvolatile memory in the storage device.

12. The system as claimed in claim 9, wherein the storage channel controller includes a store cache module, coupled to the write page module, the store cache module configured to generate a controller cache data parity to write to a non-volatile memory device, wherein the controller cache data parity is for the cache page.

13. The system as claimed in claim 9, wherein the signal empty module configured to generate the sleep signal to shut down the host bus adapter generates the sleep signal to shut down the host bus adapter after the cache write command is executed.

14. The system as claimed in claim 9, wherein the storage channel controller includes:

a controller abort read module, coupled to the de-glitch module, the controller abort read module configured to abort a read command based on the detected power failure event; and

a stop recycle module, coupled to the controller abort read module, the stop recycle module configured to abort a wear leveling operation after the read command is aborted.