System, method, and computer program product for translating a common hardware database into a logic code model

• US 9,171,115 B2
• Filed: 04/10/2013
• Issued: 10/27/2015
• Est. Priority Date: 04/10/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Alfieri, Robert Anthony
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US13/860,480
• Publication Number:
  US 20140310665A1
• Time in Patent Office: 930 Days
• Field of Search: 716100-108
• US Class Current: 1/1
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based common representation of a hardware design stored in a hardware model database. Logic code is generated for each hardware module node of the graph-based common representation of the hardware design. Additionally, flow control code is generated for each hardware module node of the graph-based common representation of the hardware design. A logic code model of the hardware design that includes the generated logic code and the generated flow control code is stored.

Claims

1. A computer program product embodied on a non-transitory computer readable medium, comprising:

code for receiving a graph-based common representation of a hardware design stored in a hardware model database, the graph-based common representation including a plurality of hardware module nodes;

code for generating logic code for each hardware module node of the graph-based common representation of the hardware design;

code for generating flow control code for each hardware module node of the graph-based common representation of the hardware design; and

code for storing a logic code model of the hardware design that includes the generated logic code and the generated flow control code, wherein a first hardware module node is either a fanout node or a fanin node, wherein the fanout node corresponds to a multicast construct or a separate construct and the fanin node corresponds to a merge construct or a select construct, wherein the hardware design is used to manufacture an integrated circuit.

2. The computer program product of claim 1, wherein the logic code model of the hardware design is represented in Verilog®

.

3. The computer program product of claim 1, further comprising code for generating an assertion check that tests whether a condition occurs during simulation of the logic code model of the hardware design.

4. The computer program product of claim 3, wherein the condition occurs when a first data input flow is valid and a second data input flow is not valid during a single clock cycle.

5. The computer program product of claim 3, wherein the condition occurs when a stall signal is asserted at an output data flow.

6. The computer program product of claim 3, wherein the generated logic code disables a clock signal when the condition occurs in an emulation environment.

7. The computer program product of claim 1, wherein the first hardware module node is the fanout node and the generated logic code replicates an input valid signal for each output data flow.

8. The computer program product of claim 1, wherein the first hardware module node is the fanin node that corresponds to the select construct, and the generated logic code produces an arbitration decision that affects the calculation of an input ready signal for each input data flow.

9. The computer program product of claim 1, wherein the first hardware module node is the fanin node and the generated logic code asserts a stall signal for each input data flow when an output data flow is stalled.

10. The computer program product of claim 1, wherein the first hardware module node is the fanin node that corresponds to the select construct, and the generated logic code implements a case statement multiplexer to select one of multiple input data flows as an output data flow.

11. The computer program product of claim 1, wherein the generated logic code includes a status bus indicating a processing state of a hardware module and the status bus indicates idle, active, or stalled.

12. The computer program product of claim 1, wherein the generated logic code includes a first-in first-out (FIFO) buffer that is coupled to an output of a hardware module.

13. The computer program product of claim 12, wherein the FIFO buffer is implemented as an asynchronous FIFO buffer when the code for generating the logic code determines that the FIFO buffer passes signals between two different clock domains.

14. The computer program product of claim 1, wherein the generated control code is based on a stallable parameter.

15. The computer program product of claim 1, further comprising code for generating logic code for clock gating at a hardware module level.

16. The computer program product of claim 1, wherein the hardware design comprises an integrated circuit design.

17. The computer program product of claim 1, further comprising code for recording a root flow referred to by a bitslice or index for an input data flow.

18. A method, comprising:

receiving a graph-based common representation of a hardware design stored in a hardware model database;

generating, by a processor, logic code for each hardware module node of the graph-based common representation of the hardware design;

generating flow control code for each hardware module node of the graph-based common representation of the hardware design; and

storing a logic code model of the hardware design that includes the generated logic code and the generated flow control code, wherein a first hardware module node is either a fanout node or a fanin node, wherein the fanout node corresponds to a multicast construct or a separate construct and the fanin node corresponds to a merge construct or a select construct, wherein the hardware design is used to manufacture an integrated circuit.

19. The method of claim 18, further comprising generating an assertion check that tests whether a condition occurs during simulation of the logic code model of the hardware design.

20. A system, comprising:

a processor for receiving a graph-based common representation of a hardware design stored in a hardware model database,

wherein the processor is configured to;

receive the graph-based common representation of a hardware design;

generate logic code for each hardware module node of the graph-based common representation of the hardware design;

generate flow control code for each hardware module node of the graph-based common representation of the hardware design; and

a memory that is coupled to the processor and configured to store a logic code model of the hardware design that includes the generated logic code and the generated flow control code, wherein a first hardware module node is either a fanout node or a fanin node, wherein the fanout node corresponds to a multicast construct or a separate construct and the fanin node corresponds to a merge construct or a select construct, wherein the hardware design is used to manufacture an integrated circuit.