Configurable memory circuit system and method

• US 9,171,585 B2
• Filed: 11/26/2013
• Issued: 10/27/2015
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastien, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Rigol, Yaima
• Application Number:
  US14/090,342
• Publication Number:
  US 20140192583A1
• Time in Patent Office: 700 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 11/4063 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Claims

1. A sub-system, comprising:

a first number of physical memory circuits including a first physical memory circuit and a second physical memory circuit, wherein each of the first number of physical memory circuits is limited by a device command scheduling constraint; and

an interface circuit electrically coupling to each one of the first number of physical memory circuits via a respective distinct bus of multiple buses including a first bus connected to the first physical memory circuit and a distinct second bus connected to the second physical memory circuit, the interface circuit configured to;

interface the first number of physical memory circuits to emulate a different, second number of virtual memory circuits, wherein the second number of virtual memory circuits includes a first virtual memory circuit emulated using at least the first physical memory circuit and the second physical memory circuit;

present the different, second number of virtual memory circuits to a memory controller, wherein the first virtual memory circuit appears to the memory controller as free from the device command scheduling constraint of the first physical memory circuit and the second physical memory circuit;

receive, from the memory controller, a row-activation command and multiple column-access commands directed to the first virtual memory circuit;

determine, based on the row activation command and the multiple column-access commands, a first physical row-activation command and a first physical column-access command directed to the first physical memory circuit and a second physical row-activation command and a second physical column-access command directed to the second physical memory circuit; and

issue, using the first bus and the second bus, the first physical row-activation command and the first physical column-access command to the first physical memory circuit and the second physical row activation command and the second physical column access command to the second physical memory circuit, wherein timings for the issued first and second physical row-activation commands and the issued first and second physical column-access commands satisfy the device command scheduling constraint.

2. The sub-system of claim 1, wherein the one or more device command scheduling constraints include inter-device command scheduling constraints.

3. The sub-system of claim 2, wherein the inter-device command scheduling constraints include at least one of a rank-to-rank data bus turnaround time or an on-die termination (ODT) control switching time.

4. The sub-system of claim 1, wherein the one or more device command scheduling constraints include intra-device command scheduling constraints.

5. The sub-system of claim 4, wherein the intra-device command scheduling constraints include at least one of a column-to-column delay time (tCCD), a row-to-row activation delay time (tRRD), a four-bank activation window time (tFAW), or a write-to-read turn-around time (tWTR).

6. The sub-system of claim 1, wherein the interface circuit includes a circuit that is positioned on a dual in-line memory module (DIMM).

7. The sub-system of claim 1, wherein the interface circuit is electrically coupled to the memory controller via a separate bus.

8. The sub-system of claim 1, wherein the first number of physical memory circuits are arranged in a stack, and the interface circuit is integrated within the stack.

9. An apparatus, comprising:

an interface circuit electrically coupling to each one of first number of physical memory circuits via a respective distinct bus of multiple buses including a first bus connected to a first physical memory circuit of the physical memory circuits and a distinct second bus connected to a second physical memory circuit of the physical memory circuits, the interface circuit configured to;

interface the first number of physical memory circuits to emulate a different, second number of virtual memory circuits, wherein the second number of virtual memory circuits includes a first virtual memory circuit emulated using at least the first physical memory circuit and the second physical memory circuit;

present the different, second number of virtual memory circuits to a memory controller, wherein the first virtual memory circuit appears to the memory controller as free from a device command scheduling constraint of the first physical memory circuit and the second physical memory circuit;

receive, from the memory controller, a row-activation command and multiple column-access commands directed to the first virtual memory circuit;

determine, based on the row activation command and the multiple column-access commands, a first physical row-activation command and a first physical column-access command directed to the first physical memory circuit and a second physical row-activation command and a second physical column-access command directed to the second physical memory circuit; and

issue, using the first bus and the second bus, the first physical row-activation command and the first physical column-access command to the first physical memory circuit and the second physical row activation command and the second physical column access command to the second physical memory circuit, wherein timings for the issued first and second physical row-activation commands and the issued first and second physical column-access commands satisfy the device command scheduling constraint.

10. The apparatus of claim 9, wherein the one or more device command scheduling constraints include inter-device command scheduling constraints.

11. The apparatus of claim 10, wherein the inter-device command scheduling constraints include at least one of a rank-to-rank data bus turnaround time or an on-die termination (ODT) control switching time.

12. The apparatus of claim 9, wherein the one or more device command scheduling constraints include intra-device command scheduling constraints.

13. The apparatus of claim 12, wherein the intra-device command scheduling constraints include at least one of a column-to-column delay time (tCCD), a row-to-row activation delay time (tRRD), a four-bank activation window time (tFAW), or a write-to-read turn-around time (tWTR).

14. The apparatus of claim 9, wherein the interface circuit is electrically coupled to the memory controller via a separate data bus.

15. The apparatus of claim 9, wherein the first number of physical memory circuits are arranged in a stack, and the interface circuit is integrated within the stack.

16. An method, comprising:

interfacing, by an interface circuit, a first number of physical memory circuits to emulate a different, second number of virtual memory circuits, wherein the second number of virtual memory circuits includes a first virtual memory circuit emulated using at least a first physical memory circuit and a second physical memory circuit of the first number of physical memory circuits;

presenting, by the interface circuit and to a memory controller, the different, second number of virtual memory circuits, wherein the first virtual memory circuit appears to the memory controller as free from a device command scheduling constraint of the first physical memory circuit and the second physical memory circuit;

receiving, by the interface circuit and from the memory controller, a row-activation command and multiple column-access commands directed to the first virtual memory circuit;

determining, by the interface circuit and based on the row activation command and the multiple column-access commands, a first physical row-activation command and a first physical column-access command directed to the first physical memory circuit and a second physical row-activation command and a second physical column-access command directed to the second physical memory circuit; and

issuing, using at least a first bus connected to the first physical memory circuit and a second bus connected to the second physical memory circuit, the first physical row-activation command and the first physical column-access command to the first physical memory circuit and the second physical row activation command and the second physical column access command to the second physical memory circuit, wherein timings for the issued first and second physical row-activation commands and the issued first and second physical column-access commands satisfy the device command scheduling constraint.

17. The method of claim 16, wherein the one or more device command scheduling constraints include inter-device command scheduling constraints.

18. The method of claim 17, wherein the inter-device command scheduling constraints include at least one of a rank-to-rank data bus turnaround time or an on die termination (ODT) control switching time.

19. The method of claim 16, wherein the one or more device command scheduling constraints include intra device command scheduling constraints.

20. The method of claim 19, wherein the intra-device command scheduling constraints include at least one of a column-to-column delay time (tCCD), a row-to-row activation delay time (tRRD), a four-bank activation window time (tFAW), or a write-to-read turn-around time (tWTR).