Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
First Claim
1. A three-dimensional (3D) memory block, comprising:
- a memory cell comprising a static random access memory (SRAM), the memory cell disposed in a first tier of a 3D integrated circuit (IC) (3DIC);
at least one read access port disposed in a second tier of the 3DIC, the at least one read access port configured to provide read access to the memory cell, wherein each read access port of the at least one read access port comprises a first read transistor coupled to a first inverter of the SRAM and a second read transistor coupled to a second inverter of the SRAM; and
at least one monolithic intertier via (MIV) coupling the at least one read access port to the memory cell.
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Abstract
A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.
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Citations
17 Claims
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1. A three-dimensional (3D) memory block, comprising:
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a memory cell comprising a static random access memory (SRAM), the memory cell disposed in a first tier of a 3D integrated circuit (IC) (3DIC); at least one read access port disposed in a second tier of the 3DIC, the at least one read access port configured to provide read access to the memory cell, wherein each read access port of the at least one read access port comprises a first read transistor coupled to a first inverter of the SRAM and a second read transistor coupled to a second inverter of the SRAM; and at least one monolithic intertier via (MIV) coupling the at least one read access port to the memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A three-dimensional (3D) memory block, comprising:
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a memory cell comprising a static random access memory (SRAM), the memory cell disposed in a first tier of a 3D integrated circuit (IC) (3DIC); at least one means for reading disposed in a second tier of the 3DIC, the at least one means for reading configured to provide read access to the memory cell, wherein each means for reading of the at least one means for reading comprises a first read transistor coupled to a first inverter of the SRAM and a second read transistor coupled to a second inverter of the SRAM; and at least one monolithic intertier via (MIV) coupling the at least one means for reading to the memory cell. - View Dependent Claims (11)
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12. A method of forming a three-dimensional (3D) memory block, comprising:
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forming a first tier of a 3D integrated circuit (IC) (3DIC); forming a memory cell comprising a static random access memory (SRAM) within the memory cell within the first tier of the 3DIC; forming a second tier of the 3DIC; forming at least one read access port within the second tier of the 3DIC, the at least one read access port configured to provide read access to the memory cell, wherein forming the at least one read access port comprises; forming a first read transistor coupled to a first inverter of the SRAM; and forming a second read transistor coupled to a second inverter of the SRAM; and coupling the at least one read access port to the memory cell with at least one monolithic intertier via (MIV). - View Dependent Claims (13, 14, 15, 16, 17)
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Specification