Resistive memory device and method programming same

• US 9,171,617 B1
• Filed: 03/25/2015
• Issued: 10/27/2015
• Est. Priority Date: 06/27/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Hyun-Kook, Lee, Yeong-Taek, Byeon, Dae-Seok, Lee, Yong-Kyu, Kwon, Hyo-Jin
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US14/667,993
• Time in Patent Office: 216 Days
• Field of Search: 365/46, 365/94, 365/100, 365/129, 365/148, 365/158, 365/163, 257 2- 5, 257/9, 257/295, 257/310, 257/E21.35, 438/95, 438/96, 438/135, 438/166, 438/240, 438/365, 438/482, 438/486, 438/597, 438/785
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse

Abstract

A method of programming memory cells of a resistive memory device includes; applying a first current pulse to each of the plurality of memory cells; applying a second current pulse that increases by a first difference compared to the first current pulse to each of the plurality of memory cells to which the first current pulse is applied; and applying a third current pulse that increases by a second difference compared to the second current pulse to each of the plurality of memory cells to which the second current pulse is applied, wherein the first through third current pulses non-linearly increase, and the second difference is greater than the first difference.

Claims

1. A method of programming memory cells of a resistive memory device, the method comprising:

performing a program operation by;

applying a first current pulse having a first amplitude to the memory cells; and

then,

applying a second current pulse having a second amplitude to the memory cells, wherein the second amplitude is greater than the first amplitude by a first current pulse difference; and

then,

applying a third current pulse having a third amplitude to the memory cells, wherein the third amplitude is greater than the second amplitude by a second current pulse difference,

wherein the second current pulse difference is greater than the first current pulse difference.

2. The method of claim 1, wherein the program operation is a set program operation, such that the applying of the first current pulse, the second current pulse and the third current pulse to memory cells causes the respective resistances exhibited by the memory cells to decrease.

3. The method of claim 2, wherein the memory cells are capable of being programmed to one of a first distribution, a second distribution, and a third distribution in response to the applying of the first current pulse, the second current pulse and the third current pulse to the memory cells, and

the method further comprises:

before applying the first current pulse, determining respective first, second and third amplitudes, such that a first current difference between a minimum current level of the first distribution and a minimum current level of the second distribution is substantially the same as a second current difference between the minimum current level of the second distribution and a minimum current level of the third distribution.

4. The method of claim 2, wherein the memory cells are capable of being programmed to one of a first distribution, a second distribution, and a third distribution in response to the applying of the first current pulse, the second current pulse and the third current pulse to the memory cells, and

the method further comprises:

before applying the first current pulse, determining the first, second and third amplitudes, such that a first resistance difference between a maximum resistance level of the first distribution and a maximum resistance level of the second distribution is substantially the same as a second resistance difference between the maximum resistance level of the second distribution and a maximum resistance level of the third distribution.

5. The method of claim 1, wherein the first current pulse has a first pulse width, the second current pulse has a second pulse width, and the third current pulse has a third pulse width,

wherein the first difference comprises at least one of a difference between the first amplitude and the second amplitude and a difference between the first pulse width and the second pulse width, and the second difference comprises at least one of a difference between the second amplitude and the third amplitude and a difference between the second pulse width and the third pulse width.

6. The method of claim 1, further comprising at least one of:

performing a verify read operation on the memory cells after applying the first current pulse to the memory cells, and performing the verify read operation on the memory cells after applying the second current pulse to the memory cells,

wherein one of the second current pulse or the third current pulse is applied at one of the memory cells that is not completely programmed in response to the performing of the verify read operation.

7. The method of claim 1, wherein each of the plurality of memory cells has one of a plurality of resistance states,

wherein the greater a resistance state difference between an initial resistance state of each of the plurality of memory cells and a target resistance state with respect to data that is to be programmed, the greater the first and second differences.

8. The method of claim 1, wherein each one of the memory cells is a resistive memory cell capable of being programmed in accordance with a plurality of resistance states, wherein the greater a resistance state difference between an initial resistance state for the memory cells and a target resistance state with respect to write data being programmed to the memory cells, the greater a non-linear increment between the first and second differences.

9. A method of operating a resistive memory device including a plurality of memory cells each having one of a plurality of resistance states, the method comprising:

determining first through Nth current pulses that non-linearly increase based on a resistance state difference between an initial resistance state of each of the plurality of memory cells and a target resistance state with respect to data that is to be programmed; and

sequentially applying the first through Nth current pulses to the plurality of memory cells,

wherein an increase range between the first through Nth current pulses increases according to an increase in an N value, and N is a natural number greater than 2.

10. The method of claim 9, wherein the first through Nth current pulses are determined in order that the greater the resistance state difference between the initial resistance state and the target resistance state, the greater an increase range between the first through Nth current pulses.

11. The method of claim 10, wherein the increase range between the first through Nth current pulses is an increase amount of at least one of amplitude and width of each of the first through Nth current pulses.

12. The method of claim 9, wherein the determining of the first through Nth current pulses comprises:

determining the second current pulse having a value that increases by a first difference compared to the first current pulse, and determining the third current pulse having a value that increases by a second difference compared to the second current pulse, wherein the second difference is greater than the first difference.

13. The method of claim 9, wherein the greater the resistance state difference, the greater N.

14. A method of programming memory cells of a resistive memory device, the method comprising:

performing a program operation by;

applying a first current pulse having a first width to the memory cells; and

then,

applying a second current pulse having a second width to the memory cells, wherein the second width is greater than the first width by a first current pulse difference; and

then,

applying a third current pulse having a third width to the memory cells, wherein the third width is greater than the second amplitude by a second current pulse difference,

wherein the second current pulse difference is greater than the first current pulse difference.

15. The method of claim 14, wherein the program operation is a set program operation, such that the applying of the first current pulse, second current pulse and the third current pulse to memory cells causes the respective resistances exhibited by the memory cells to decrease.

16. The method of claim 14, wherein the program operation is a reset program operation, such that the applying of the first current pulse, second current pulse and the third current pulse to memory cells causes the respective resistances exhibited by the memory cells to increase.

17. The method of claim 15, wherein the memory cells are capable of being programmed to one of a first distribution, a second distribution, and a third distribution in response to the applying of the first current pulse, the second current pulse and the third current pulse to the memory cells, and

the method further comprises:

before applying the first current pulse, determining respective first, second and third amplitudes, such that a first current difference between a minimum current level of the first distribution and a minimum current level of the second distribution is substantially the same as a second current difference between the minimum current level of the second distribution and a minimum current level of the third distribution.

18. The method of claim 14, further comprising at least one of:

performing a verify read operation on the memory cells after applying the first current pulse to the memory cells, and performing the verify read operation on the memory cells after applying the second current pulse to the memory cells,

wherein one of the second current pulse or the third current pulse is applied at one of the memory cells that is not completely programmed in response to the performing of the verify read operation.

19. The method of claim 14, wherein each of the plurality of memory cells has one of a plurality of resistance states, and

the greater a resistance state difference between an initial resistance state of each of the plurality of memory cells and a target resistance state with respect to data that is to be programmed, the greater the first and second differences.

20. The method of claim 14, wherein each one of the memory cells is a resistive memory cell capable of being programmed in accordance with a plurality of resistance states, wherein the greater a resistance state difference between an initial resistance state for the memory cells and a target resistance state with respect to write data being programmed to the memory cells, the greater a non-linear increment between the first and second differences.