Reducing weak-erase type read disturb in 3D non-volatile memory

• US 9,171,632 B2
• Filed: 11/04/2013
• Issued: 10/27/2015
• Est. Priority Date: 02/02/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dong, Yingda, Mui, Man L, Miwa, Hitoshi
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Huang, Min
• Application Number:
  US14/071,288
• Publication Number:
  US 20140056065A1
• Time in Patent Office: 722 Days
• Field of Search: 365/185.17
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.

Claims

1. A method for operating a 3D stacked non-volatile memory device comprising multiple levels of memory cells in a stack, the method comprising:

performing a read operation for a selected memory cell in a selected string of the memory device, the performing a read operation comprises applying a control gate voltage to a selected word line layer of the memory device which is connected to the selected memory cell, while providing a drain-side select gate of the selected string in a conductive state, and while sensing a threshold voltage of the selected memory cell; and

controlling a boosting level of a channel of an unselected string in the memory device during the read operation, the controlling comprises allowing boosting of the channel followed by interrupting boosting of the channel, the allowing boosting of the channel comprise applying an increasing pass voltage to an unselected word line layer of the memory device while providing drain-side and source-side select gates of the unselected string in a non-conductive state, and the interrupting boosting of the channel comprises transitioning at least one of the drain-side and source-side select gates of the unselected string from the non-conductive state to the conductive state.

2. The method of claim 1, wherein:

the controlling comprises transitioning the at least one of the drain-side and source-side select gates of the unselected string back from the conductive state to the non-conductive state.

3. The method of claim 2, further comprising:

further increasing the pass voltage after the transitioning the at least one of the drain-side and source-side select gates of the unselected string back from the conductive state to the non-conductive state.

4. The method of claim 2, wherein:

the transitioning the at least one of the drain-side and source-side select gates of the unselected string from the non-conductive state to the conductive state comprises increasing a voltage of the at least one of the drain-side and source-side select gates of the unselected string.

5. The method of claim 4, further comprising:

transitioning the at least one of the drain-side and source-side select gates of the unselected string from the conductive state back to the non-conductive state by decreasing the voltage of the at least one of the drain-side and source-side select gates of the unselected string.

6. The method of claim 5, wherein:

the voltage of the at least one of the drain-side and source-side select gates of the unselected string has a spike shape.

7. The method of claim 5, wherein:

the voltage of the at least one of the drain-side and source-side select gates of the unselected string reaches a steady state level after the increasing the voltage and before the decreasing the voltage.

8. The method of claim 1, wherein:

the transitioning comprises transitioning both the drain-side and source-side select gates of the unselected string from the non-conductive state to the conductive state.

9. The method of claim 8, wherein:

the controlling comprises transitioning both the drain-side and source-side select gates of the unselected string back from the conductive state to the non-conductive state.

10. The method of claim 1, wherein:

the performing the read operation comprises providing a source-side select gate of the selected string in the conductive state.

11. The method of claim 1, wherein:

the controlling comprise applying the increasing pass voltage to a plurality of unselected word line layers of the memory device.

12. The method of claim 1, further comprising:

during the transitioning, applying a voltage to the selected word line layer which is sufficiently high to render the selected memory cell in the conductive state.

13. The method of claim 12, further comprising:

after the transitioning and before the sensing, removing the voltage from the selected word line layer which is sufficiently high to render the selected memory cell in the conductive state.

14. The method of claim 1, further comprising:

while providing the drain-side select gate of the selected string in the conductive state, applying, via a common bit line, a non-zero voltage to the drain-side select gate of the selected string and to the drain-side select gate of the unselected string.

15. A 3D stacked non-volatile memory device, comprising:

multiple levels of memory cells formed on a substrate, the memory cells in the multiple levels of memory cells comprise a selected memory cell in a selected level of the multiple levels and in a selected string of memory cells, and unselected memory cells in the multiple levels and in an unselected string of memory cells, the selected string comprising a drain-side select gate and a source-side select gate, and the unselected string comprising a drain-side select gate and a source-side select gate; and

a control circuit, the control circuit provides an increase during a period of time in a pass voltage for memory cells in an unselected level of the multiple levels, and during the period of time, provides the drain-side select gate of the selected string in a conductive state and transitions at least one of the drain-side select gate and the source-side select gate from a non-conductive state to the conductive state and back to the non-conductive state, and after the period of time, applies a control gate voltage to the selected memory cell and senses a threshold voltage of the selected memory cell.

16. The 3D stacked non-volatile memory device of claim 15, wherein:

during the period of time, the control circuit applies a voltage to the selected level which is sufficiently high to render the selected memory cell in the conductive state.

17. The 3D stacked non-volatile memory device of claim 16, wherein:

during the period of time, the control circuit removes the voltage from the selected level which is sufficiently high to render the selected memory cell in the conductive state.

18. The 3D stacked non-volatile memory device of claim 15, wherein:

the selected and unselected strings comprise U-shaped NAND strings or straight NAND strings.

19. A method for performing a read operation in a 3D stacked non-volatile memory device comprising multiple levels of memory cells, the method comprising:

boosting a channel of an unselected string of memory cells, the memory cells in the multiple levels of memory cells comprise a selected string of memory cells and the unselected string of memory cells, the selected string of memory cells comprises a selected memory cell in a selected level of the multiple levels, a drain-side select gate and a source-side select gate, and the unselected string comprises a drain-side select gate and a source-side select gate, the boosting the channel comprises increasing a pass voltage for memory cells in unselected levels of the multiple levels from an initial level to an elevated level;

during the increasing of the pass voltage, before the pass voltage reaches the elevated level, interrupting the boosting by raising a voltage of the drain-side select gate of the unselected string, causing the drain-side select gate of the unselected string to transition from a non-conductive state to a conductive state; and

with the channel at a boosted level caused by the boosting, and the pass voltage at the elevated level;

applying a control gate read voltage to the selected memory cell, and sensing whether a threshold voltage of the at least one of the selected memory cells is above the control gate read voltage.

20. The method of claim 19, further comprising:

during the increasing of the pass voltage, transitioning the drain-side select gate of the unselected string back from the conductive state to the non-conductive state.