Reducing weak-erase type read disturb in 3D non-volatile memory
First Claim
1. A method for operating a 3D stacked non-volatile memory device comprising multiple levels of memory cells in a stack, the method comprising:
- performing a read operation for a selected memory cell in a selected string of the memory device, the performing a read operation comprises applying a control gate voltage to a selected word line layer of the memory device which is connected to the selected memory cell, while providing a drain-side select gate of the selected string in a conductive state, and while sensing a threshold voltage of the selected memory cell; and
controlling a boosting level of a channel of an unselected string in the memory device during the read operation, the controlling comprises allowing boosting of the channel followed by interrupting boosting of the channel, the allowing boosting of the channel comprise applying an increasing pass voltage to an unselected word line layer of the memory device while providing drain-side and source-side select gates of the unselected string in a non-conductive state, and the interrupting boosting of the channel comprises transitioning at least one of the drain-side and source-side select gates of the unselected string from the non-conductive state to the conductive state.
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Abstract
A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.
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Citations
20 Claims
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1. A method for operating a 3D stacked non-volatile memory device comprising multiple levels of memory cells in a stack, the method comprising:
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performing a read operation for a selected memory cell in a selected string of the memory device, the performing a read operation comprises applying a control gate voltage to a selected word line layer of the memory device which is connected to the selected memory cell, while providing a drain-side select gate of the selected string in a conductive state, and while sensing a threshold voltage of the selected memory cell; and controlling a boosting level of a channel of an unselected string in the memory device during the read operation, the controlling comprises allowing boosting of the channel followed by interrupting boosting of the channel, the allowing boosting of the channel comprise applying an increasing pass voltage to an unselected word line layer of the memory device while providing drain-side and source-side select gates of the unselected string in a non-conductive state, and the interrupting boosting of the channel comprises transitioning at least one of the drain-side and source-side select gates of the unselected string from the non-conductive state to the conductive state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A 3D stacked non-volatile memory device, comprising:
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multiple levels of memory cells formed on a substrate, the memory cells in the multiple levels of memory cells comprise a selected memory cell in a selected level of the multiple levels and in a selected string of memory cells, and unselected memory cells in the multiple levels and in an unselected string of memory cells, the selected string comprising a drain-side select gate and a source-side select gate, and the unselected string comprising a drain-side select gate and a source-side select gate; and a control circuit, the control circuit provides an increase during a period of time in a pass voltage for memory cells in an unselected level of the multiple levels, and during the period of time, provides the drain-side select gate of the selected string in a conductive state and transitions at least one of the drain-side select gate and the source-side select gate from a non-conductive state to the conductive state and back to the non-conductive state, and after the period of time, applies a control gate voltage to the selected memory cell and senses a threshold voltage of the selected memory cell. - View Dependent Claims (16, 17, 18)
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19. A method for performing a read operation in a 3D stacked non-volatile memory device comprising multiple levels of memory cells, the method comprising:
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boosting a channel of an unselected string of memory cells, the memory cells in the multiple levels of memory cells comprise a selected string of memory cells and the unselected string of memory cells, the selected string of memory cells comprises a selected memory cell in a selected level of the multiple levels, a drain-side select gate and a source-side select gate, and the unselected string comprises a drain-side select gate and a source-side select gate, the boosting the channel comprises increasing a pass voltage for memory cells in unselected levels of the multiple levels from an initial level to an elevated level; during the increasing of the pass voltage, before the pass voltage reaches the elevated level, interrupting the boosting by raising a voltage of the drain-side select gate of the unselected string, causing the drain-side select gate of the unselected string to transition from a non-conductive state to a conductive state; and with the channel at a boosted level caused by the boosting, and the pass voltage at the elevated level;
applying a control gate read voltage to the selected memory cell, and sensing whether a threshold voltage of the at least one of the selected memory cells is above the control gate read voltage. - View Dependent Claims (20)
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Specification