Shift register and display device

• US 9,171,640 B2
• Filed: 10/04/2010
• Issued: 10/27/2015
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyake, Hiroyuki, Amano, Seiko
• Primary Examiner(s): Bost, Dwayne
• Assistant Examiner(s): MICHAUD, ROBERT J
• Application Number:
  US12/897,375
• Publication Number:
  US 20110084960A1
• Time in Patent Office: 1,849 Days
• Field of Search: 345/100
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/0285 using tables for spatial correction of display data
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The shift register includes first to fourth flip-flops. A first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input to the first flip-flop. A second clock signal which is in the first voltage state in the second period and in the second voltage state in the third period and the fourth period is input to the second flip-flop. A third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input to the third flip-flop. A fourth clock signal which is in the second voltage state in the first and second periods and in the first voltage state in the fourth period is input to the fourth flip-flop.

Claims

1. A shift register comprising:

a first flip-flop to which a first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input;

a second flip-flop to which a second clock signal which is in the first voltage state in at least part of the second period and in the second voltage state in at least part of the third period, and the fourth period is input;

a third flip-flop to which a third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input;

a fourth flip-flop to which a fourth clock signal which is in the second voltage state in at least part of the first period, and the second period and in the first voltage state in at least part of the fourth period is input;

a first to fourth clock signal lines;

a first power supply line to which a high power supply voltage is applied; and

a second power supply line to which a low power supply voltage is applied,

wherein each of the first to fourth flip-flops comprises;

a first transistor comprising a gate, a source and a drain,

wherein a start signal is input to the gate of the first transistor, and

wherein one of the source and the drain of the first transistor is electrically connected to the first power supply line;

a second transistor comprising a gate, a source and a drain,

wherein the gate of the second transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of the source and the drain of the second transistor is electrically connected to one of the first to fourth clock signal lines, and

wherein an output signal is output from the other of the source and the drain of the second transistor;

a third transistor comprising a gate, a source and a drain,

wherein one of the source and the drain of the third transistor is electrically connected to the gate of the second transistor, and

wherein the other of the source and the drain of the third transistor is electrically connected to the second power supply line; and

a fourth transistor comprising a gate, a source and a drain,

wherein the gate of the fourth transistor is directly connected to the gate of the third transistor.

2. The shift register according to claim 1, wherein the first to third transistors have a same conductivity type.

3. The shift register according to claim 1, wherein each of the first to third transistors comprises an oxide semiconductor layer serving as a channel formation layer.

4. A display device comprising:

a driver circuit comprising the shift register according to claim 1; and

a pixel portion comprising a pixel whose display state is controlled by the driver circuit.

5. A method for driving a shift register comprising a first to fourth flip-flops;

a first to fourth clock signal lines;

a first power supply line to which a high power supply voltage is applied; and

a second power supply line to which a low power supply voltage is applied, the method comprising;

inputting a first clock signal, which is in a first voltage state in a first period and in a second voltage state in second to fourth periods, to the first flip-flop;

inputting a second clock signal, which is in the first voltage state in at least part of the second period and in the second voltage state in at least part of the third period, and the fourth period, to the second flip-flop;

inputting a third clock signal, which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period, to the third flip-flop; and

inputting a fourth clock signal, which is in the second voltage state in at least part of the first period, and the second period and in the first voltage state in at least part of the fourth period, to the fourth flip-flop,

wherein each of the first to fourth flip-flops comprises;

a first transistor comprising a gate, a source and a drain,

wherein a start signal is input to the gate of the first transistor, and

wherein one of the source and the drain of the first transistor is electrically connected to the first power supply line;

a second transistor comprising a gate, a source and a drain,

wherein the gate of the second transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of the source and the drain of the second transistor is electrically connected to one of the first to fourth clock signal lines, and

wherein an output signal is output from the other of the source and the drain of the second transistor;

a third transistor comprising a gate, a source and a drain,

wherein one of the source and the drain of the third transistor is electrically connected to the gate of the second transistor, and

wherein the other of the source and the drain of the third transistor is electrically connected to the second power supply line; and

a fourth transistor comprising a gate, a source and a drain,

wherein the gate of the fourth transistor is directly connected to the gate of the third transistor.

6. The shift register according to claim 5, wherein the first to third transistors have a same conductivity type.

7. The shift register according to claim 5, wherein each of the first to third transistors comprises an oxide semiconductor layer serving as a channel formation layer.

8. A display device comprising:

a driver circuit comprising the shift register according to claim 5; and

a pixel portion comprising a pixel whose display state is controlled by the driver circuit.

9. A shift register comprising:

a first flip-flop to which a first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input;

a second flip-flop to which a second clock signal which is in the first voltage state in at least part of the second period and in the second voltage state in at least part of the third period, and the fourth period is input;

a third flip-flop to which a third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input;

a fourth flip-flop to which a fourth clock signal which is in the second voltage state in at least part of the first period, and the second period and in the first voltage state in at least part of the fourth period is input;

a first to fourth clock signal lines;

a first power supply line to which a high power supply voltage is applied; and

a second power supply line to which a low power supply voltage is applied,

wherein each of the first to fourth flip-flops comprises;

a first transistor comprising a gate, a source and a drain,

wherein a start signal is input to the gate of the first transistor, and

wherein one of the source and the drain of the first transistor is electrically connected to the first power supply line;

a second transistor comprising a gate, a source and a drain,

wherein the gate of the second transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of the source and the drain of the second transistor is electrically connected to one of the first to fourth clock signal lines, and

wherein an output signal is output from the other of the source and the drain of the second transistor;

a third transistor comprising a gate, a source and a drain,

wherein one of the source and the drain of the third transistor is electrically connected to the gate of the second transistor, and

wherein the other of the source and the drain of the third transistor is electrically connected to the second power supply line; and

a fourth transistor comprising a gate, a source and a drain,

wherein the gate of the fourth transistor is directly connected to the gate of the third transistor,

wherein one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, and

wherein the other of the source and the drain of the fourth sixth transistor is electrically connected to the second power supply line.

10. The shift register according to claim 9, wherein the first to fourth sixth transistors have a same conductivity type.

11. The shift register according to claim 9, wherein each of the first to fourth sixth transistors comprises an oxide semiconductor layer serving as a channel formation layer.

12. A display device comprising:

a driver circuit comprising the shift register according to claim 9; and

a pixel portion comprising a pixel whose display state is controlled by the driver circuit.