Method for forming a power semiconductor device

• US 9,171,728 B2
• Filed: 04/24/2014
• Issued: 10/27/2015
• Est. Priority Date: 07/26/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Mauder, Anton, Schulze, Hans-Joachim, Hirler, Franz, Lehnert, Wolfgang, Berger, Rudolf, Pruegl, Klemens, Strack, Helmut
• Primary Examiner(s): ULLAH, ELIAS
• Application Number:
  US14/260,352
• Publication Number:
  US 20140235058A1
• Time in Patent Office: 551 Days
• Field of Search: 438/268, 257/328, 257/546, 257/E29.006, 257/E21.41
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02109 characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
• CPC Class Codes: H01L 21/02145 the material containing aluminium, e.g. AlSiOx
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/8611 : Planar PN junction diodes

Abstract

A method for forming a semiconductor device includes providing a semiconductor body which has a main surface and a first n-type semiconductor region, forming a trench which extends from the main surface into the first n-type semiconductor region, and forming a dielectric layer having fixed negative charges on a surface of the trench, by performing at least one atomic layer deposition using an organometallic precursor.

Claims

1. A method for forming a semiconductor device, the method comprising:

providing a semiconductor body which comprises a main surface and a first n-type semiconductor region;

forming a trench which extends from the main surface into the first n-type semiconductor region; and

forming a dielectric layer comprising fixed negative charges on a surface of the trench, comprising performing at least one atomic layer deposition using an organometallic precursor.

2. The method of claim 1, wherein a monolayer of metal organyls is formed by the atomic layer deposition.

3. The method of claim 1, wherein performing the at least one atomic layer deposition further comprises cleaving of ligands of the organometallic precursor.

4. The method of claim 1, further comprising forming a metal-doped silicon oxide layer.

5. The method of claim 1, wherein an aluminum organyl is used as the organometallic precursor.

6. The method of claim 1, wherein trimethyl aluminum is used as the organometallic precursor.

7. The method of claim 1, further comprising forming a starting oxide layer on the surface of the trench prior to performing the at least one atomic layer deposition.

8. The method of claim 1, wherein a charge carrier density per area of the fixed negative charges of the dielectric layer decreases step-wise or continuously with increasing distance from the main surface.

9. The method of claim 1, further comprising partially masking the trench prior to performing the at least one atomic layer deposition.

10. The method of claim 1, wherein the dielectric layer is formed such that the dielectric layer has a negative positive net charge, the method further comprising:

forming at least one further trench which extends from the main surface into the semiconductor body; and

forming on a surface of the at least one further trench a further dielectric layer having a positive net charge.