Embedding thin chips in polymer

• US 9,171,794 B2
• Filed: 03/15/2013
• Issued: 10/27/2015
• Est. Priority Date: 10/09/2012
• Status: Active Grant

• Current Assignee: Medidata Solutions Incorporated (Dassault Systemes SA)
• Original Assignee: MC10, Inc.
• Inventors: Rafferty, Conor, Dalal, Mitul
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US13/844,638
• Publication Number:
  US 20140110859A1
• Time in Patent Office: 956 Days
• Field of Search: 257/678, 257/713, 257/774, 257/792, 257/E23.065, 257/E23.177, 257/668, 257/723, 438/118, 438/27, 438/29, 438/106, 438/107, 438/113, 438/127
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/03436 Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/036 by patterning a pre-deposited material
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/8203 : Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2224/83132 : using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/8314 : Guiding structures outside the body
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/16 : Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H05K 1/0283 : Stretchable printed circuits
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/189 : characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2203/1469 : Circuit made after mounting or encapsulation of the components

Abstract

Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.

Claims

1. An apparatus comprising:

A) a substrate comprising a standoff well region, wherein;

the substrate comprises a layer of a first conductive material disposed on a layer of a flexible polymer, wherein the flexible polymer is further stretchable; and

a patterned portion of the first conductive material comprises a standoff bordering a portion of exposed flexible polymer, thereby forming the standoff well region;

B) a thin chip disposed within the standoff well region on a portion of the exposed flexible polymer proximate to the standoff; and

C) an adhesive material disposed within the standoff well region at a portion of the exposed flexible polymer proximate to the standoff, the thin chip being disposed on the adhesive material proximate the standoff, the adhesive material including a conductive adhesive,

wherein a height of the standoff is comparable to a height of the thin chip.

2. The apparatus of claim 1, wherein the adhesive material has a thickness of about 8 μ

m, about 10 μ

m, about 12 μ

m, about 15 μ

m, about 20 μ

m, about 25 μ

m, or about 30 μ

m.

3. The apparatus of claim 1, wherein the patterned portion of the first conductive material is formed using laser ablation or etching.

4. The apparatus of claim 1, wherein the first conductive material comprises copper, gold, aluminum, or some combination thereof.

5. The apparatus of claim 1, wherein the layer of flexible polymer has a thickness of about 8 μ

m, about 10 μ

m, about 15 μ

m, about 25 μ

m, about 35 μ

m, about 50 μ

m, about 60 μ

m, about 75 μ

m, or about 85 μ

m.

6. The apparatus of claim 1, wherein the layer of first conductive material has a thickness of about 2 μ

m, about 5 μ

m, about 8 μ

m, about 12 μ

m, about 15 μ

m, about 25 μ

m, about 35 μ

m, about 50 μ

m, about 60 μ

m, or about 70 μ

m.

7. The apparatus of claim 1, wherein the thin chip has a thickness of about 2 μ

m, about 5 um, about 8 μ

m, about 12 μ

m, about 15 μ

m, about 25 μ

m, about 35 μ

m, about 50 μ

m, about 60 μ

m, or about 70 μ

m.

8. The apparatus of claim 1, wherein the thin chip is a thinned chip.

9. The apparatus of claim 8, wherein the thinned chip is formed from a chip that is thinned using an etching process or a grinding process.

10. The apparatus of claim 1, wherein the thin chip is disposed within the standoff well region such that the height of the standoff is greater than or about equal to the height of the thin chip.

11. The apparatus of claim 1, wherein the thin chip is disposed within the standoff well region such that the height of the standoff is less than the height of the thin chip.

12. The apparatus of claim 1, wherein the thin chip includes a layer of first conductive material having a thickness of about 2 μ

m, about 5 um, about 8 μ

m, about 12 um, about 15 vim, about 25 um, about 35 pm, about 50 μ

m, about 60 μ

m, or about 70 μ

m.

13. The apparatus of claim 1, further comprising:

a polymer sheet disposed over the substrate;

at least one via formed through the polymer sheet; and

a second conductive material disposed on a portion of the polymer sheet proximate to the at least one via, such that the second conductive material forms an electrical communication with an electrical contact of the thin chip.

14. The apparatus of claim 13, wherein the second conductive material comprises titanium, tungsten, gold, nickel, chromium, or some combination thereof.

15. The apparatus of claim 1, wherein the standoff surrounds a portion of the thin chip.

16. The apparatus of claim 1, wherein the standoff completely surrounds the thin chip.

17. The apparatus of claim 1, wherein a dielectric material is disposed between the standoff and a portion of the thin chip.

18. The apparatus of claim 1, further comprising at least one additional layer disposed on the first conductive material or on the flexible polymer, wherein the at least one additional layer positions the thin chip at a neutral mechanical plane of the apparatus.

19. The apparatus of claim 1, wherein the flexible polymer includes a polyurethane.

20. The apparatus of claim 1, wherein the flexible polymer includes an elastomer or an elastoplastic.

21. The apparatus of claim 20, wherein flexible polymer includes a thermoplastic elastomer.

22. The apparatus of claim 20, wherein the flexible polymer includes a silicone elastomer.

23. The apparatus of claim 1, wherein the standoff includes a plurality of standoffs that define the standoff well region, the standoff configured to border at least three sides of the thin chip.

24. The apparatus of claim 23, wherein the standoff includes at least one gap between the plurality of standoffs that define the standoff well region.

25. The apparatus of claim 1, wherein the standoff includes a plurality of standoffs that define the standoff well region, the standoff being configured to border all sides of the thin chip, the standoff further including at least one gap between the plurality of standoffs that define the standoff well region.

26. A method for embedding thin chips, the method comprising:

A) providing a substrate comprising a standoff well region, wherein;

the substrate comprises a layer of a first conductive material disposed on a layer of a flexible polymer, wherein the flexible polymer is further stretchable; and

at least a portion of the first conductive material is patterned to form a standoff bordering a portion of exposed flexible polymer, thereby forming the standoff well region;

B) disposing a conductive adhesive material within the standoff well region at a portion of the exposed flexible polymer proximate to the standoff; and

C) disposing a thin chip on a portion of the exposed flexible polymer proximate to the standoff such that a height of the standoff is comparable to a height of the thin chip, the thin chip being disposed on the conductive adhesive material proximate to the standoff.

27. The method of claim 26, wherein the height of the standoff is greater than or about equal to a height of a thin chip.

28. The method of claim 26, wherein C) comprises disposing the thin chip on a portion of the flexible polymer proximate to the standoff such that the height of the standoff is greater than or about equal to the height of the thin chip.

29. The method of claim 26, wherein the thin chip is a thinned chip, and wherein C) comprises thinning a chip using an etching process or a grinding process to provide the thinned chip, and disposing the thinned chip on a portion of the exposed flexible polymer proximate to the standoff such that a height of the standoff is comparable to a height of the thinned chip.

30. The method of claim 26, further comprising:

disposing a polymer sheet over the substrate;

forming at least one via through the polymer sheet; and

disposing a conductive material on a portion of the second polymer sheet proximate to the at least one via, such that the conductive material forms an electrical communication with an electrical contact of the thin chip.

31. The method of claim 26, further comprising disposing at least one additional layer on the first conductive material or on the flexible polymer, wherein the at least one additional layer positions the thin chip at a neutral mechanical plane of the apparatus.

32. An apparatus comprising:

A) a substrate comprising a polymer well region, wherein;

the substrate comprises a layer of a flexible polymer disposed on a layer of a first conductive material, wherein the flexible polymer is further stretchable;

a cavity is formed in at least a portion of the flexible polymer to form at least one polymer wall bordering a portion of exposed first conductive material, thereby forming the polymer well region;

B) a thin chip disposed within the polymer well region on at least a portion of the exposed first conductive material proximate to the at least one polymer wall; and

C) an adhesive material disposed within the polymer well region at a portion of the exposed first conductive material proximate to the at least one polymer wall, the adhesive material including a conductive adhesive, the thin chip being disposed on the adhesive material proximate to the at least one polymer wall.

33. The apparatus of claim 32, wherein the adhesive material has a thickness of about 8 μ

m, about 10 μ

m, about 12 μ

m, about 15 μ

m, about 20 μ

m, about 25 μ

m, or about 30 μ

m.

34. The apparatus of claim 32, wherein the cavity is formed using laser ablation or etching.

35. The apparatus of claim 32, wherein the first conductive material comprises copper, gold, aluminum, or some combination thereof.

36. The apparatus of claim 32, wherein the layer of flexible polymer has a thickness of about 8 μ

m, about 10 μ

m, about 15 μ

m, about 25 μ

m, about 35 μ

m, about 50 μ

m, about 60 μ

m, about 75 μ

m, or about 85 μ

m.

37. The apparatus of claim 32, wherein the layer of first conductive material has a thickness of about 2 μ

m, about 5 μ

m, about 8 μ

m, about 12 μ

m, about 15 μ

m, about 25 μ

m, about 35 μ

m, about 50 μ

m, about 60 μ

m, or about 70 μ

m.

38. The apparatus of claim 32, wherein the thin chip has a thickness of about 2 μ

m, about 5 μ

m, about 8 μ

m, about 12 μ

m, about 15 μ

m, about 25 μ

m, about 35 μ

m, about 50 μ

m, about 60 μ

m, or about 70 μ

m.

39. The apparatus of claim 38, wherein the thinned chip is formed from a chip that is thinned using an etching process or a grinding process.

40. The apparatus of claim 32, wherein the thin chip is a thinned chip.

41. The apparatus of claim 32, wherein the thin chip is disposed within the polymer well region such that the height of the at least one polymer wall is greater than or about equal to the height of the thin chip.

42. The apparatus of claim 32, wherein the thin chip is disposed within the polymer well region such that the height of the at least one polymer wall is less than the height of the thin chip.

43. The apparatus of claim 32, wherein the thin chip has a layer of first conductive material has a thickness of about 2 μ

m, about 5 μ

m, about 8 μ

m, about 12 μ

m, about 15 μ

m, about 25 μ

m, about 35 μ

m, about 50 μ

m, about 60 μ

m, or about 70 μ

m.

44. The apparatus of claim 32, further comprising:

a polymer sheet disposed over the substrate;

at least one via formed through the polymer sheet; and

a second conductive material disposed on a portion of the polymer sheet proximate to the at least one via, such that the second conductive material forms an electrical communication with an electrical contact of the thin chip.

45. The apparatus of claim 44, wherein the second conductive material comprises titanium, tungsten, gold, nickel, chromium, or some combination thereof.

46. The apparatus of claim 32, wherein the at least one polymer wall surrounds a portion of the thin chip.

47. The apparatus of claim 32, wherein the at least one polymer wall completely surrounds the thin chip.

48. The apparatus of claim 32, wherein a dielectric material is disposed between the at least one polymer wall and a portion of the thin chip.

49. The apparatus of claim 32, further comprising at least one additional layer disposed on the first conductive material or on the flexible polymer, wherein the at least one additional layer positions the thin chip at a neutral mechanical plane of the apparatus.

50. The apparatus of claim 32, wherein the thin chip is a thinned chip, and wherein B) comprises thinning a chip using an etching process or a grinding process to provide the thinned chip, and disposing the thinned chip within the polymer well region on at least a portion of the exposed first conductive material proximate to the at least one polymer wall such that a height of the least one wall is comparable to a height of the thinned chip.

51. A method for embedding thin chips, the method comprising:

A) providing a substrate comprising a polymer well region, the substrate comprising a layer of a flexible polymer and a layer of a first conductive material, the flexible polymer further being stretchable, the polymer well region comprising at least one polymer wall formed from a portion of the flexible polymer and a base region formed from at least a portion of the first conductive material;

B) disposing an adhesive material at the portion of the first conductive proximate to the at least one polymer wall, the adhesive material including a conductive adhesive; and

C) disposing the thin chip within the polymer well region on a portion of the first conductive material proximate to the at least one polymer wall, the thin chip being disposed on the adhesive material proximate to the at least one polymer wall.

52. The method of claim 51, wherein the thin chip is disposed within the polymer well region such that the height of the at least one polymer wall is greater than or about equal to the height of the thin chip.

53. The method of claim 51, wherein the thin chip is disposed within the polymer well region such that the height of the at least one polymer wall is less than the height of the thin chip.

54. The method of claim 51, wherein the thin chip is disposed within the polymer well region such that the first conductive material is in physical and electrical communication with the thin chip.

55. The method of claim 51, further comprising:

a polymer sheet disposed over the substrate;

at least one via formed through the polymer sheet; and

a second conductive material disposed on a portion of the polymer sheet proximate to the at least one via, such that the second conductive material forms an electrical communication with an electrical contact of the thin chip.

56. The method of claim 51, further comprising disposing at least one additional layer on the first conductive material or on the flexible polymer, wherein the at least one additional layer positions the thin chip at a neutral mechanical plane of the apparatus.