Escape routes

• US 9,171,809 B2
• Filed: 03/05/2014
• Issued: 10/27/2015
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: Flextronics America LLC (Flextronics International Limited)
• Original Assignee: Flextronics America LLC (Flextronics International Limited)
• Inventors: Lopez, Omar Garcia, Ahumada Quintero, Pedro Alejandro, Secada, Enrique Avelar, Kurwa, Murad, Gonzalez, Juan Carlos
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US14/198,399
• Publication Number:
  US 20140312479A1
• Time in Patent Office: 601 Days
• Field of Search: 257/669, 438/106
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/26122 being formed on the semiconductor or solid-state body to be connected
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/83815 Reflow soldering
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1011 Structure
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate
• CPC Class Codes: H05K 2201/10969 Metallic case or integral heatsink of component electrically connected to a pad on PCB
• CPC Class Codes: H05K 2203/1178 Means for venting or for letting gases escape
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3452 Solder masks
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Methods of and devices for providing escaping routes for the flux and gases generated to move away from the solder joint in the process of solder joint formation.

Claims

1. A device comprising:

a. a computing chip physically coupled with a printed circuit board; and

b. a first fluid channel on a body of the computing chip coupled with a second fluid channel on the printed circuit board forming a connected fluid channel allowing a fluid to come out from a space beneath the computer chip to the printed circuit board.

2. The device of claim 1, wherein the fluid comprises flux.

3. The device of claim 1, wherein the fluid comprises an amount of gas.

4. The device of claim 1, wherein the fluid is generated when a heat is applied.

5. The device of claim 1, wherein the heat is applied at a reflow process.

6. The device of claim 1, wherein the fluid channel comprises a pressure relief mechanism.

7. The device of claim 1, wherein the computing chip comprises a bottom terminal component.

8. A semiconductor assembly comprising a first fluidic pressure relief structure on a body of a printed circuit board fluidically coupling with a second fluidic pressure relief structure on a body of the computing chip allowing a fluid to come out from a space beneath a computer chip to the printed circuit board.

9. The assembly of claim 8, wherein the structure comprises one or more fluid channels.

10. The assembly of claim 8, wherein the one or more fluid channels are at a corner of the semiconductor assembly.

11. The assembly of claim 8, wherein the one or more fluid channels are at a side of the semiconductor assembly.

12. The assembly of claim 8, wherein the assembly comprises dual flat no-lead (DFN), land grid array (LGA), or pull-back quad flat no-lead (PQFN).

13. The assembly of claim 8, wherein the fluidic pressure is generated when a heat is applied.

14. The assembly of claim 13, wherein the heat comprises a reflow process.

15. The assembly of claim 8, wherein the fluidic pressure is generated by an amount of gas within the assembly.

16. The assembly of claim 8, wherein the fluidic pressure is generated by an amount of flux within the assembly.

17. A method of preventing pressure building up in a semiconductor packaging comprising:

a. providing one or more aperture in the semiconductor chip;

b. providing a pressure relief structure on a printed circuit board coupling with the one or more aperture in the semiconductor chip; and

c. allowing a fluid to be released from the one or more aperture in the semiconductor chip to the pressure relief structure on the printed circuit board when a heat is applied.

18. The method of claim 17, wherein the aperture comprises a channel.

19. The method of claim 17, wherein the fluid comprises a flux.

20. The method of claim 17, wherein the fluid comprises an amount of gas.