Isolation structure in gallium nitride devices and integrated circuits
First Claim
1. An integrated semiconductor device comprising:
- a buffer layer disposed on a substrate layer;
a gallium nitride layer disposed on the buffer layer;
a barrier layer disposed on the gallium nitride layer;
a plurality of first device contacts for a first transistor device formed on a first portion of an exposed surface of the barrier layer;
a plurality of second device contacts for a second transistor device formed on a second portion of the exposed surface of the barrier layer;
at least one gate structure formed on a third portion of the surface of the barrier,wherein the gate structure is disposed between the plurality of first device contacts and the plurality of second device contacts to form an isolation region of the integrated semiconductor device that electrically isolates the first transistor device from the second transistor device.
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Accused Products
Abstract
An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.
22 Citations
26 Claims
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1. An integrated semiconductor device comprising:
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a buffer layer disposed on a substrate layer; a gallium nitride layer disposed on the buffer layer; a barrier layer disposed on the gallium nitride layer; a plurality of first device contacts for a first transistor device formed on a first portion of an exposed surface of the barrier layer; a plurality of second device contacts for a second transistor device formed on a second portion of the exposed surface of the barrier layer; at least one gate structure formed on a third portion of the surface of the barrier, wherein the gate structure is disposed between the plurality of first device contacts and the plurality of second device contacts to form an isolation region of the integrated semiconductor device that electrically isolates the first transistor device from the second transistor device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An integrated semiconductor device comprising:
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a buffer layer disposed on a substrate layer; a gallium nitride layer disposed on the buffer layer; a barrier layer disposed on the gallium nitride layer; a plurality of first device contacts for a first transistor device formed on a first portion of an exposed surface of the barrier layer; a plurality of second device contacts for a second transistor device formed on a second portion of the exposed surface of the barrier layer; a pair of gate structures formed on a third portion of the surface of the barrier, wherein the pair of gate structures are disposed between the plurality of first device contacts and the plurality of second device contacts to form an isolation region of the integrated semiconductor device that electrically isolates the first transistor device from the second transistor device. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification