Edge termination configurations for high voltage semiconductor power devices

• US 9,171,917 B2
• Filed: 01/23/2014
• Issued: 10/27/2015
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur, Lui, Sik, Bhalla, Anup
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US14/162,220
• Publication Number:
  US 20150206943A1
• Time in Patent Office: 642 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

Claims

1. A method to manufacture a semiconductor power device in a semiconductor substrate with an active cell area and an edge termination area comprising:

open a wide trench in the edge termination area immediately adjacent to a body region disposed on an outer edge of the active cell area and filling the wide trench with a field-crowding reduction filler followed by etching the field-crowding reduction filler down to a level below a top surface of said wide trench; and

forming a buried field plate along a sidewall of said wide trench and extending vertically along the body region on the outer edge of the active area and cover a top surface of said field-crowing reduction filler followed by filling the wide trench with the field-crowding reduction filler thus burying the buried field plate in the wide trench below the top surface of the trench.

2. The method of claim 1 wherein:

the step of filling the wide trench with the field-crowding reduction filler comprises a step of filling the wide trench with silicon oxide.

3. The method of claim 1 wherein:

the step of opening the wide trench in the edge termination area further comprising a step of opening the wide trench with a width ranging from 5 microns to 50 microns in the edge termination area having a width ranging from 10 microns to 60 microns.

4. The method of claim 1 wherein:

the step of etching the field-crowding reduction filler down to a level below a top surface of said wide trench further comprising a step of etching the field-crowding reduction filler down to a depth ranging from 1.5 microns to 5 microns below the top surface of the wide trench.

5. The method of claim 1 wherein:

the step of opening the wide trench in the edge termination area further comprising a step of opening a plurality of narrow trenches in the edge termination area followed by oxidizing the semiconductor substrate between the narrow trenches to function as the field-crowding reduction filler then filling the narrow trenches by depositing the field-crowding reduction filler.

6. The method of claim 1 wherein:

the step of forming the buried field plate is a step of forming the buried under the top surface of the semiconductor substrate and above a depletion region at a bottom surface of the body region; and

the step of etching the field-crowding reduction filler down to a level below a top surface of said wide trench further comprising a step of etching the field-crowding reduction filler down to a depth above a depletion region at a bottom surface of the body region.

7. The method of claim 1 wherein:

the buried field plate is buried under the top surface of the semiconductor substrate and above a depletion region at a bottom surface of the body region; and

the step of etching the field-crowding reduction filler down to a level below a top surface of said wide trench further comprising a step of etching the field-crowding reduction filler down to a depth below a depletion region at a bottom surface of the body region.

8. The method of claim 1 wherein:

the step of forming the buried field plate further comprises a step of forming the buried field plate with a top portion covering a part of a top surface of the body region and a vertical portion extends vertically downward along the sidewall of the wide trench to connected to the buried field plate buried in the wide trench.