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Semiconductor device including superjunction structure formed using angled implant process

  • US 9,171,949 B1
  • Filed: 09/24/2014
  • Issued: 10/27/2015
  • Est. Priority Date: 09/24/2014
  • Status: Active Grant
First Claim
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1. A method for forming a semiconductor device comprising:

  • providing a heavily doped semiconductor substrate of a first conductivity type;

    forming a buffer layer of the first conductivity type on the semiconductor substrate;

    forming a semiconductor layer of a second conductivity type on the buffer layer;

    forming a plurality of trenches in the semiconductor layer, the trenches extending close to, up to, or into the buffer layer, the trenches forming mesas in the semiconductor layer;

    performing a first ion implantation of dopants of the first conductivity type directed to sidewall surfaces of the plurality of trenches, the ion implantation being performed at an angle relative to the central vertical axis of the trenches and using a first implant energy;

    forming a first epitaxial layer on the sidewall surface of the plurality of trenches;

    performing a second ion implantation of dopants of the first conductivity type directed to sidewall surfaces of the plurality of trenches, the ion implantation being performed at an angle relative to the central vertical axis of the trenches and using a second implant energy;

    performing a third ion implantation of dopants of the second conductivity type directed to sidewall surfaces of the plurality of trenches, the ion implantation being performed at an angle relative to the central vertical axis of the trenches and using a third implant energy, wherein the second implant energy is greater than the third implant energy, and the dopants of the second conductivity type having a diffusion rate greater than the diffusion rate of the dopants of the first conductivity type;

    forming a second epitaxial layer on the sidewall surfaces of the plurality of trenches after the ion implantation;

    annealing the implanted dopants to form first and second thin semiconductor regions of the first conductivity type interleaved and sandwiched between third thin semiconductor regions of the second conductivity type, the first, second and third thin semiconductor regions being formed near the trench sidewall surface of the mesas; and

    forming a first dielectric layer in the trenches, the first dielectric layer filling at least part of the trenches,wherein the first and second thin semiconductor regions together have a first thickness and a first doping concentration, the third thin semiconductor regions interleaving and bordering the first and second thin semiconductor regions on both sides having a second thickness and a second doping concentration, the first and second thicknesses and the first and second doping concentrations being selected to achieve charge balance in operation.

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