Semiconductor device including superjunction structure formed using angled implant process

• US 9,171,949 B1
• Filed: 09/24/2014
• Issued: 10/27/2015
• Est. Priority Date: 09/24/2014
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Padmanabhan, Karthik, Bobde, Madhur, Guan, Lingpeng, Zhang, Lei, Yilmaz, Hamza
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Tran, Dzung
• Application Number:
  US14/495,817
• Time in Patent Office: 398 Days
• Field of Search: 257/337, 257/341, 257/139, 257/328, 257/493, 257/266, 257/330, 257/332, 257/339, 257/471, 257/480, 257/E21.551, 257/E29.257, 438/197, 438/700
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device.

Claims

1. A method for forming a semiconductor device comprising:

providing a heavily doped semiconductor substrate of a first conductivity type;

forming a buffer layer of the first conductivity type on the semiconductor substrate;

forming a semiconductor layer of a second conductivity type on the buffer layer;

forming a plurality of trenches in the semiconductor layer, the trenches extending close to, up to, or into the buffer layer, the trenches forming mesas in the semiconductor layer;

performing a first ion implantation of dopants of the first conductivity type directed to sidewall surfaces of the plurality of trenches, the ion implantation being performed at an angle relative to the central vertical axis of the trenches and using a first implant energy;

forming a first epitaxial layer on the sidewall surface of the plurality of trenches;

performing a second ion implantation of dopants of the first conductivity type directed to sidewall surfaces of the plurality of trenches, the ion implantation being performed at an angle relative to the central vertical axis of the trenches and using a second implant energy;

performing a third ion implantation of dopants of the second conductivity type directed to sidewall surfaces of the plurality of trenches, the ion implantation being performed at an angle relative to the central vertical axis of the trenches and using a third implant energy, wherein the second implant energy is greater than the third implant energy, and the dopants of the second conductivity type having a diffusion rate greater than the diffusion rate of the dopants of the first conductivity type;

forming a second epitaxial layer on the sidewall surfaces of the plurality of trenches after the ion implantation;

annealing the implanted dopants to form first and second thin semiconductor regions of the first conductivity type interleaved and sandwiched between third thin semiconductor regions of the second conductivity type, the first, second and third thin semiconductor regions being formed near the trench sidewall surface of the mesas; and

forming a first dielectric layer in the trenches, the first dielectric layer filling at least part of the trenches,

wherein the first and second thin semiconductor regions together have a first thickness and a first doping concentration, the third thin semiconductor regions interleaving and bordering the first and second thin semiconductor regions on both sides having a second thickness and a second doping concentration, the first and second thicknesses and the first and second doping concentrations being selected to achieve charge balance in operation.

2. The method of claim 1, further comprising:

forming a body region of the second conductivity type in a top portion of at least a first mesa of the semiconductor layer;

forming a gate dielectric layer on the first mesa of the semiconductor layer above the body region;

forming a gate conductive layer above the gate dielectric layer as the gate electrode; and

forming a heavily doped source region of the first conductivity type in the body region aligned to the gate conductive layer,

wherein a lateral MOSFET is formed with the semiconductor substrate being a drain region, the first and second thin semiconductor regions being a drain drift region, the channel region of the lateral MOSFET being formed in the body region between the source region and the drain drift region.

3. The method of claim 1, performing the second ion implantation of dopants of the first conductivity type directed to the sidewall surfaces of the plurality of trenches comprises:

performing the second ion implantation of dopants using the second implant energy to implant dopants near a surface of the first epitaxial layer and separate and away from the dopants from the first ion implantation.

4. The method of claim 1, performing the first ion implantation, the second ion implantation and the third ion implantation of dopants comprises:

performing the first, second and third ion implantation of dopants without performing any annealing in between the ion implantations.

5. The method of claim 1, wherein annealing the implanted dopants to form first and second thin semiconductor regions of the first conductivity type comprises:

annealing the implanted dopants of the first conductivity type to form the first and second thin semiconductor regions of the first conductivity type, the buffer layer out-diffusing into the mesa of the semiconductor layer to electrically connect the first and second thin semiconductor regions to the semiconductor substrate.

6. The method of claim 1, wherein annealing the implanted dopants to form first and second thin semiconductor regions of the first conductivity type and the third thin semiconductor regions of the second conductivity type comprises:

annealing the implanted dopants of the first conductivity type to form the first and second thin semiconductor regions of the first conductivity type at a position close to where the dopants are implanted; and

annealing the implanted dopants of the second conductivity type to cause the dopants to spread out and diffuse into the mesas past the implanted dopants of the first ion implantation to form the third thin semiconductor regions of the second conductivity type interleaving and bordering the first and second thin semiconductor regions on both sides.

7. The method of claim 1, wherein the first conductivity type comprises N-type conductivity and the second conductivity type comprises P-type conductivity.

8. The method of claim 7, wherein the dopants of the first conductivity type comprises arsenic and the dopants of the second conductivity type comprises boron.

9. The method of claim 1, wherein the first conductivity type comprises P-type conductivity and the second conductivity type comprises N-type conductivity.

10. The method of claim 1, wherein performing the first, second and third ion implantations of dopants of respective first and second conductivity types directed to the sidewall surfaces of the plurality of trenches comprises:

performing the first, second and third ion implantations at an angle relative to the central vertical axis of the trenches, the angle being less than 20 degrees.

11. The method of claim 1, wherein performing the first, second and third ion implantations of dopants of the respective first and second conductivity types directed to the sidewall surfaces of the plurality of trenches comprises:

forming implanted dopants of the second conductivity type in the mesas and near the sidewall surface of the trenches;

forming first implanted dopants of the first conductivity type in the mesas and deeper from the sidewall surface of the trenches as compared to the implanted dopants of the second conductivity type; and

forming second implanted dopants of the first conductivity type in the mesas and deeper from the sidewall surface of the trenches as compared to the first implanted dopants of the first conductivity type.

12. The method of claim 1, wherein forming the first epitaxial layer on the sidewall surface of the plurality of trenches comprises:

forming the first epitaxial layer being an undoped epitaxial layer.

13. The method of claim 1, wherein forming a second epitaxial layer on the sidewall surfaces of the plurality of trenches after the ion implantation comprises:

forming the second epitaxial layer being undoped or lightly doped of the first or second conductivity type.

14. The method of claim 1, wherein forming a plurality of trenches in the semiconductor layer comprises:

forming the plurality of trenches in the semiconductor layer having tapered sidewall, the sidewall of the mesas having an angle of less than perpendicular with the buffer layer.