Semiconductor structure having aperture antenna

• US 9,172,131 B2
• Filed: 03/15/2013
• Issued: 10/27/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chen, Chi-Han, Chiu, Chi-Tsung
• Primary Examiner(s): Nguyen, Hoang V
• Application Number:
  US13/834,424
• Publication Number:
  US 20140266947A1
• Time in Patent Office: 956 Days
• Field of Search: 343/700.MS
• US Class Current: 1/1
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 21/0093 Monolithic arrays
• CPC Class Codes: H01Q 21/065 Patch antenna array
• CPC Class Codes: H01Q 9/0457 electromagnetically coupled to the feed line

Abstract

The semiconductor package includes a first substrate having a first surface and a second surface opposite to the first surface. A circuit portion is formed on the first surface of the substrate, wherein the circuit portion includes a wave guiding slot and a microstrip line overlapping the wave guiding slot. A chip is disposed on the circuit portion. An antenna is formed on the second surface of the substrate, wherein the antenna overlaps the wave guiding slot.

Claims

1. A semiconductor structure comprising:

a substrate having a first surface and a second surface opposite to the first surface;

a circuit portion formed on the first surface of the substrate and comprising a wave guiding slot and a microstrip line overlapped with the wave guiding slot;

a chip disposed on the circuit portion wherein the microstrip line is positioned in the circuit portion outside a footprint of the chip; and

an antenna formed on the second surface of the substrate and overlapped with the wave guiding slot.

2. The semiconductor structure of claim 1, wherein the circuit portion comprises a grounding layer overlapping the chip.

3. The semiconductor structure of claim 2, wherein the wave guiding slot is formed on the grounding layer.

4. The semiconductor structure of claim 2, wherein each of the grounding layer, the substrate, and the circuit portion has an outer lateral surface, the outer lateral surface of the grounding layer, the outer lateral surface of the substrate and the outer lateral surface of the circuit portion being flush with each other.

5. The semiconductor structure of claim 1, wherein the circuit portion has a plurality of the wave guiding slots which are not overlapped with the chip.

6. The semiconductor structure of claim 1, wherein an extension direction of the microstrip line is substantially perpendicular to that of the wave guiding slot.

7. The semiconductor structure of claim 1, wherein the antenna overlaps the wave guiding slot.

8. The semiconductor structure of claim 1, wherein the substrate is made from glass.

9. The semiconductor structure of claim 1, wherein the circuit portion comprises:

a first dielectric layer formed between the grounding layer and the microstrip line.

10. The semiconductor structure of claim 1, further comprising:

an antenna dielectric layer formed on the second surface of the substrate and covering the antenna.

11. A semiconductor structure comprising:

a substrate having a first surface and a second surface opposite to the first surface;

an integrated passive layer formed on the first surface of the substrate, comprising a plurality of wave guiding slots and a plurality of microstrip lines overlapped with the wave guiding slots, wherein the wave guiding slots and the microstrip lines are arranged in a form of an array;

a chip disposed on the integrated passive layer, wherein the microstrip lines are positioned in the integrated passive layer outside a footprint of the chip; and

a plurality of antennas formed on the second surface of the substrate and overlapping the wave guiding slots.

12. The semiconductor structure of claim 11, wherein the integrated passive layer comprises a grounding layer overlapping the chip.

13. The semiconductor structure of claim 12, wherein the wave guiding slots are formed on the grounding layer.

14. The semiconductor structure of claim 12, wherein each of the grounding layer, the substrate, and the integrated passive layer has an outer lateral surface, the outer lateral surface of the grounding layer, the outer lateral surface of the substrate, and the outer lateral surface of the integrated passive layer are flush with each other.

15. The semiconductor structure of claim 11, wherein the integrated passive layer has a plurality of the wave guiding slots which are not overlapped with the chip.

16. The semiconductor structure of claim 11, wherein an extension direction of each microstrip line is substantially perpendicular to that of the corresponding wave guiding slot.

17. The semiconductor structure of claim 11, wherein the antennas overlap the wave guiding slots.

18. The semiconductor structure of claim 11, wherein the substrate is made from glass.

19. The semiconductor structure of claim 11, wherein the integrated passive layer comprises:

a first dielectric layer formed between the grounding layer and the microstrip lines.

20. The semiconductor structure of claim 11, further comprising an antenna dielectric layer formed on the second surface of the substrate and covering the antennas.