Semiconductor integrated circuit

• US 9,172,237 B2
• Filed: 05/15/2012
• Issued: 10/27/2015
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sato, Takehisa
• Primary Examiner(s): Kitov, Zeev V
• Application Number:
  US13/471,638
• Publication Number:
  US 20120293893A1
• Time in Patent Office: 1,260 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H02H 5/044 using a semiconductor device to sense the temperature
• CPC Class Codes: H02M 1/327 against abnormal temperatures
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H03K 2017/0806 against excessive temperature

Abstract

A power source circuit includes a voltage converter circuit and a control circuit that includes a voltage divider circuit and a protective circuit. The protective circuit includes a first oxide semiconductor transistor in which an off-state current is increased as temperature is increased, a capacitor that accumulates the off-state current as electric charge, a second oxide semiconductor transistor, and an operational amplifier including a non-inverting input terminal to which a reference voltage is input. The first oxide semiconductor transistor is provided near the voltage converter circuit or an element that generates heat in the control circuit.

Claims

1. A circuit comprising:

a voltage converter circuit comprising a third transistor; and

a control circuit comprising;

an error amplifier;

a pulse width modulation output driver, an input terminal of the pulse width modulation output driver being electrically connected to an output terminal of the error amplifier, and an output terminal of the pulse width modulation output driver being electrically connected to a gate of the third transistor; and

a protective circuit, the protective circuit comprising;

a first transistor comprising an oxide semiconductor layer in a channel region;

a capacitor;

a second transistor comprising an oxide semiconductor layer in a channel region; and

an operational amplifier comprising a non-inverting input terminal to which a reference voltage is input,

wherein one of a source and a drain of the first transistor is electrically connected to a terminal of the capacitor, one of a source and a drain of the second transistor, and an inverting input terminal of the operational amplifier, and

wherein an element that generates heat in the voltage converter circuit or the control circuit is detected by the first transistor adjacent to the element.

2. The circuit according to claim 1, wherein an off-state current of the first transistor increases as an increase of a temperature of the first transistor.

3. The circuit according to claim 2, wherein the capacitor is configured to accumulate the off-state current of the first transistor as an electric charge.

4. The circuit according to claim 1, wherein the first transistor and the element are arranged in a multi-finger layout or a common-centroid layout.

5. The circuit according to claim 1, further comprising a voltage divider circuit electrically connected to the voltage converter circuit.

6. The circuit according to claim 1, wherein the control circuit further comprises:

a voltage regulator circuit electrically connected to the other of the source and the drain of the first transistor, the voltage regulator circuit being configured to adjust an output voltage;

a bias generation circuit electrically connected to the voltage regulator circuit, the bias generation circuit being configured to be applied a bias voltage or a bias current;

a reference voltage generation circuit electrically connected to the voltage regulator circuit, the reference voltage generation circuit being configured to generate a second reference voltage; and

a band gap reference electrically connected to the voltage regulator circuit, the band gap reference being configured to generate a third reference voltage.

7. The circuit according to claim 1, wherein the voltage converter circuit is a DC-DC converter.

8. The circuit according to claim 1, wherein the voltage converter circuit is an AC-DC converter.

22. The circuit according to claim 1, wherein the oxide semiconductor layer of each of the first transistor and the second transistor comprises at least one of indium and zinc.

23. The circuit according to claim 1, wherein a channel width of the first transistor is larger than a channel width of the second transistor.

24. The circuit according to claim 1, wherein a voltage input to a gate of the first transistor is lower than or equal to 0V.

9. A circuit comprising:

a voltage converter circuit comprising a third transistor;

an error amplifier;

a pulse width modulation output driver, an input terminal of the pulse width modulation output driver being electrically connected to an output terminal of the error amplifier, and an output terminal of the pulse width modulation output driver being electrically connected to a gate of the third transistor;

a first transistor comprising an oxide semiconductor layer in a channel region;

a capacitor; and

an operational amplifier comprising a non-inverting input terminal to which a reference voltage is input,

wherein one of a source and a drain of the first transistor is electrically connected to a terminal of the capacitor and an inverting input terminal of the operational amplifier, and

wherein the capacitor is configured to accumulate an off-state current of the first transistor as an electric charge so that the accumulated voltage is input to the inverting input terminal.

10. The circuit according to claim 9, wherein the off-state current of the first transistor increases as an increase of a temperature of the first transistor.

11. The circuit according to claim 9, further comprising a second transistor comprising an oxide semiconductor layer in a channel region,

wherein one of a source and a drain of the second transistor is electrically connected to the terminal of the capacitor.

12. The circuit according to claim 9,

wherein the voltage converter circuit comprises an element, and

wherein the element is adjacent to the first transistor.

13. The circuit according to claim 12, wherein the first transistor and the element are arranged in a multi-finger layout or a common-centroid layout.

14. The circuit according to claim 9, wherein the voltage converter circuit is a DC-DC converter.

15. The circuit according to claim 9, wherein the voltage converter circuit is an AC-DC converter.

25. The circuit according to claim 9, wherein the oxide semiconductor layer of the first transistor comprises at least one of indium and zinc.

26. The circuit according to claim 9, wherein a voltage input to a gate of the first transistor is lower than or equal to 0V.

16. A circuit comprising:

a voltage converter circuit comprising a third transistor;

an error amplifier;

a pulse width modulation output driver, an input terminal of the pulse width modulation output driver being electrically connected to an output terminal of the error amplifier, and an output terminal of the pulse width modulation output driver being electrically connected to a gate of the third transistor;

a first transistor comprising an oxide semiconductor layer in a channel region;

a capacitor;

a second transistor comprising an oxide semiconductor layer in a channel region; and

an operational amplifier comprising a non-inverting input terminal to which a reference voltage is input,

wherein one of a source and a drain of the first transistor is electrically connected to a terminal of the capacitor, one of a source and a drain of the second transistor, and an inverting input terminal of the operational amplifier,

wherein a ground potential is input to the other of the source and the drain of the second transistor,

wherein the capacitor is configured to accumulate an off-state current of the first transistor as an electric charge, and

wherein the second transistor is capable of releasing the electric charge accumulated in the capacitor.

17. The circuit according to claim 16, wherein the off-state current of the first transistor increases as an increase of a temperature of the first transistor.

18. The circuit according to claim 16,

wherein the voltage converter circuit comprises an element, and

wherein the element is adjacent to the first transistor.

19. The circuit according to claim 18, wherein the first transistor and the element are arranged in a multi-finger layout or a common-centroid layout.

20. The circuit according to claim 16, wherein the voltage converter circuit is a DC-DC converter.

21. The circuit according to claim 16, wherein the voltage converter circuit is an AC-DC converter.

27. The circuit according to claim 16, wherein the oxide semiconductor layer of each of the first transistor and the second transistor comprises at least one of indium and zinc.

28. The circuit according to claim 16, wherein a channel width of the first transistor is larger than a channel width of the second transistor.

29. The circuit according to claim 16, wherein a voltage input to a gate of the first transistor is lower than or equal to 0V.