Induction-coupled clock distribution for an integrated circuit
First Claim
1. An integrated circuit package, comprising:
- a transmission module, including a transmission coil, coupled to a main clock line;
a semiconductor die;
a clock reception module including a reception coil and a clock output line, the reception coil disposed on the semiconductor die and inductively coupled to the transmission coil of the transmission module to generate a clocking signal on the clock output line;
an electronic circuit disposed on the semiconductor die and coupled to the clock output line of the clock reception module, the electronic circuit comprising at least one clocked element, and configured to operate synchronously with the clocking signal received through the clock output line of the clock reception module; and
a supporting case configured to enclose the semiconductor die, the supporting case comprising the transmission module in a plane parallel and above the semiconductor die.
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Accused Products
Abstract
An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.
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Citations
20 Claims
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1. An integrated circuit package, comprising:
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a transmission module, including a transmission coil, coupled to a main clock line; a semiconductor die; a clock reception module including a reception coil and a clock output line, the reception coil disposed on the semiconductor die and inductively coupled to the transmission coil of the transmission module to generate a clocking signal on the clock output line; an electronic circuit disposed on the semiconductor die and coupled to the clock output line of the clock reception module, the electronic circuit comprising at least one clocked element, and configured to operate synchronously with the clocking signal received through the clock output line of the clock reception module; and a supporting case configured to enclose the semiconductor die, the supporting case comprising the transmission module in a plane parallel and above the semiconductor die. - View Dependent Claims (2, 3, 4, 5, 6, 7, 18, 19)
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8. An integrated circuit package comprising:
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a semiconductor die; a supporting case configured to enclose the semiconductor die; a transmission module coupled to a main clock line and disposed on a plane of the supporting case parallel to the semiconductor die along the perimeter of the supporting case; a plurality of clock reception modules inductively coupled to the transmission module and disposed on the semiconductor die, each clock reception module comprising a clock output line; and a plurality of electronic circuits disposed on the semiconductor die, each electronic circuit coupled to the clock output line of a corresponding clock reception module of the plurality of clock reception modules, each electronic circuit comprising at least one clocked element and configured to operate synchronously with a clocking signal received through the corresponding clock output line; wherein at least one electronic circuit of the plurality of electronic circuits comprises a buffer amplifier coupled to the clock output line of the corresponding clock reception module and coupled to the at least one clocked element of the at least one electronic circuit. - View Dependent Claims (9, 10, 11, 12)
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13. An integrated circuit package, comprising:
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a semiconductor die; a supporting case configured to enclose the semiconductor die; a plurality of clock reception modules disposed on the semiconductor die, each clock reception module comprising a clock output line; a plurality of transmission modules coupled to a main clock line, disposed on a plane of the supporting case parallel to the semiconductor die, and each transmission module of the plurality of transmission modules inductively coupled to at least one clock reception module of the plurality of clock reception modules; and a plurality of electronic circuits disposed on the semiconductor die, each electronic circuit coupled to the clock output line of a corresponding clock reception module of the plurality of clock reception modules, each electronic circuit comprising at least one clocked element and configured to operate synchronously with a clocking signal received through the corresponding clock output line; wherein one of a phase lock loop unit and a voltage controlled oscillator is coupled to the main clock line. - View Dependent Claims (14, 15, 16, 17, 20)
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Specification