Methods and apparatus to reduce signaling power

• US 9,172,567 B2
• Filed: 11/25/2013
• Issued: 10/27/2015
• Est. Priority Date: 11/25/2013
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Hollis, Timothy Mowry
• Primary Examiner(s): Haider, Syed
• Application Number:
  US14/089,683
• Publication Number:
  US 20150146816A1
• Time in Patent Office: 701 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: H03M 5/02 Conversion to or from representation by pulses
• CPC Class Codes: H04L 25/4915 using pattern inversion or substitution H04L25/4908 takes precedence
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.

Claims

1. A data communications method, comprising:

determining a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state;

generating transmission symbols from the plurality of input data symbols, wherein the primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and the secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; and

providing the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link.

2. The method of claim 1, wherein generating transmission symbols from the plurality of input data symbols includes:

inverting the primary bits of the input data symbols when the first fraction is greater than a half; and

inverting the secondary bits of the input data symbols when the second fraction is greater than a half.

3. The method of claim 1, wherein generating transmission symbols from the plurality of input data symbols includes:

inverting the primary bits of the transmission symbols when the first fraction is greater than a half or the second fraction is greater than a half.

4. The method of claim 1, wherein the primary bits and secondary bits are binary-encoded bits of a multi-bit data symbol, and wherein more power is required to transmit a binary-encoded bit in the first logic state than to transmit a binary-encoded bit in a second logic state.

5. The method of claim 1, further comprising:

transmitting a sequence of the transmission symbols on a connector of the communications link.

6. The method of claim 1, further comprising:

transmitting the transmission symbols in parallel on the communications link.

7. The method of claim 1, further comprising:

providing an encoding indicator signal to one of the one or more multi-state encoders to obtain a multi-level encoding indicator signal indicating whether the primary bits of the transmission symbols correspond to the secondary bits of the input data symbols and the secondary bits of the transmission symbols correspond to the primary bits of the input data symbols.

8. The method of claim 7, further comprising:

transmitting the multi-level encoding indicator signal and the multi-level transmission symbols in parallel in one transmission clock cycle on the communications link.

9. The method of claim 7, wherein the multi-level encoding indicator signal indicates whether the primary bits of the transmission symbols are inverted.

10. The method of claim 7, wherein the multi-level encoding indicator signal indicates whether the secondary bits of the transmission symbols are inverted.

11. The method of claim 1, wherein the one or more multi-state encoders encode each of the transmission symbols as one of at least 3 voltage or current levels.

12. The method of claim 1, wherein the one or more multi-state encoders encode each of the transmission symbols for transmission on a pulse amplitude modulated communications link.

13. An apparatus, comprising:

means for determining a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state;

means for generating transmission symbols from the plurality of input data symbols, wherein the primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and the secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; and

means for providing the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link.

14. The apparatus of claim 13, wherein the means for generating transmission symbols from the plurality of input data symbols is configured to:

invert the primary bits of the input data symbols when the first fraction is greater than a half; and

invert the secondary bits of the input data symbols when the second fraction is greater than a half.

15. The apparatus of claim 13, wherein the means for generating transmission symbols from the plurality of input data symbols is configured to:

invert the primary bits of the transmission symbols when the first fraction is greater than a half or the second fraction is greater than a half.

16. The apparatus of claim 13, wherein the primary bits and secondary bits are binary-encoded bits of a multi-bit data symbol, and wherein more power is required to transmit a binary-encoded bit in the first logic state than to transmit a binary-encoded bit in a second logic state.

17. The apparatus of claim 13, further comprising:

means for transmitting a sequence of the transmission symbols on a connector of the communications link.

18. The apparatus of claim 13, further comprising:

means for transmitting the transmission symbols in parallel on the communications link.

19. The apparatus of claim 13, further comprising:

means for providing an encoding indicator signal to one of the one or more multi-state encoders to obtain a multi-level encoding indicator signal indicating whether the primary bits of the transmission symbols correspond to the secondary bits of the input data symbols and the secondary bits of the transmission symbols correspond to the primary bits of the input data symbols.

20. The apparatus of claim 19, further comprising:

means for transmitting the multi-level encoding indicator signal and the multi-level transmission symbols in parallel in one transmission clock cycle on the communications link.

21. The apparatus of claim 19, wherein the multi-level encoding indicator signal indicates whether the primary bits of the transmission symbols are inverted.

22. The apparatus of claim 19, wherein the multi-level encoding indicator signal indicates whether the secondary bits of the transmission symbols are inverted.

23. The apparatus of claim 13, wherein the one or more multi-state encoders are configured to encode each of the transmission symbols as one of at least 3 voltage or current levels.

24. The apparatus of claim 13, wherein the one or more multi-state encoders are configured to encode each of the transmission symbols for transmission on a pulse amplitude modulated communications link.

25. An apparatus, comprising:

one or more multi-state encoders configured to encode transmission symbols as multi-level transmission symbols for transmission on a pulse amplitude modulated communications link;

a processing circuit configured to;

determine a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state;

generate the transmission symbols from the plurality of input data symbols, wherein the primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and the secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; and

provide the transmission symbols to the one or more multi-state encoders.

26. The apparatus of claim 25, wherein the processing circuit is configured to generate transmission symbols from the plurality of input data symbols by:

inverting the primary bits of the input data symbols when the first fraction is greater than a half; and

inverting the secondary bits of the input data symbols when the second fraction is greater than a half.

27. The apparatus of claim 25, wherein the processing circuit is configured to generate transmission symbols from the plurality of input data symbols by:

inverting the primary bits of the transmission symbols when the first fraction is greater than a half or the second fraction is greater than a half.

28. The apparatus of claim 25, wherein the primary bits and secondary bits are binary-encoded bits of a multi-bit data symbol, and wherein more power is required to transmit a binary-encoded bit in the first logic state than to transmit a binary-encoded bit in a second logic state.

29. The apparatus of claim 25, wherein the processing circuit is configured to:

cause a sequence of the transmission symbols to be transmitted on a connector of the communications link.

30. The apparatus of claim 25, wherein the processing circuit is configured to:

cause the transmission symbols to be transmitted in parallel on the communications link.

31. The apparatus of claim 25, wherein the processing circuit is configured to:

provide an encoding indicator signal to one of the one or more multi-state encoders to obtain a multi-level encoding indicator signal indicating whether the primary bits of the transmission symbols correspond to the secondary bits of the input data symbols and the secondary bits of the transmission symbols correspond to the primary bits of the input data symbols.

32. The apparatus of claim 31, wherein the processing circuit is configured to:

cause the multi-level encoding indicator signal and the multi-level transmission symbols to be transmitted in parallel in one transmission clock cycle on the communications link.

33. The apparatus of claim 31, wherein the multi-level encoding indicator signal indicates whether the primary bits of the transmission symbols are inverted.

34. The apparatus of claim 31, wherein the multi-level encoding indicator signal indicates whether the secondary bits of the transmission symbols are inverted.

35. The apparatus of claim 25, wherein the one or more multi-state encoders encode each of the transmission symbols as one of at least 3 voltage or current levels.

36. The apparatus of claim 25, wherein the one or more multi-state encoders encode each of the transmission symbols for transmission on a pulse amplitude modulated communications link.

37. A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

determine a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state;

generate transmission symbols from the plurality of input data symbols, wherein the primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and the secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; and

provide the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link.

38. The non-transitory processor-readable storage medium of claim 37, wherein the instructions cause the at least one processing circuit to:

invert the primary bits of the transmission symbols when the first fraction is greater than a half or the second fraction is greater than a half.

39. The non-transitory processor-readable storage medium of claim 37, wherein the instructions cause the at least one processing circuit to:

provide an encoding indicator signal to one of the one or more multi-state encoders to obtain a multi-level encoding indicator signal indicating whether the primary bits of the transmission symbols correspond to the secondary bits of the input data symbols and the secondary bits of the transmission symbols correspond to the primary bits of the input data symbols.

40. The non-transitory processor-readable storage medium of claim 39, wherein the multi-level encoding indicator signal indicates whether the primary bits of the transmission symbols are inverted, and whether the secondary bits of the transmission symbols are inverted.

41. A method performed by a device, comprising:

decoding, via a decoding circuit, a multi-level encoding indicator signal received from a communications link to provide a plurality of control signals;

selectively inverting, via an inverting circuit, a primary bit of data symbols decoded from one or more signals received from the communications link based on a first of the plurality of control signals;

selectively inverting, via the inverting circuit, a secondary bit of the data symbols based on a second of the plurality of control signals; and

selectively swapping, via a swapping circuit, the primary bit and the secondary bit based on a third of the plurality of control signals,

wherein more power is required to transmit the primary bit or the secondary bit in a first logic state than in a second logic state.

42. The method of claim 41, wherein swapping the primary bit and the secondary bit includes:

providing a version of the primary bit of each symbol decoded from the one or more signals as a secondary bit of an output symbol; and

providing a version of the secondary bit of each symbol decoded from the one or more signals as a primary bit of the output symbol.

43. The method of claim 41, wherein the encoding indicator signal and the one or more signals received from the communications link include pulse amplitude modulation signals having at least 3 levels.

44. The method of claim 41, wherein the first logic state and the second logic state correspond to different boolean logic levels.

45. An apparatus, comprising:

a multi-state decoder configured to decode a multi-level encoding indicator signal received from a communications link and to provide a plurality of control signals extracted from the encoding indicator signal; and

a processing circuit configured to;

selectively invert a primary bit of data symbols decoded from one or more signals received from the communications link based on a first of the plurality of control signals;

selectively invert a secondary bit of the data symbols based on a second of the plurality of control signals; and

selectively swap the primary bit and the secondary bit based on a third of the plurality of control signals,

wherein more power is required to transmit the primary bit or the secondary bit in a first logic state than in a second logic state.

46. The apparatus of claim 45, wherein the processing circuit is configured to swap the primary bit and the secondary bit by:

providing a version of a primary bit of each symbol decoded from the one or more signals as a secondary bit of an output symbol; and

providing a version of a secondary bit of each symbol decoded from the one or more signals as a primary bit of the output symbol.

47. The apparatus of claim 45, wherein the processing circuit is configured to swap the primary bit and the secondary bit by:

providing a version of the primary bit of each symbol decoded from the one or more signals as a secondary bit of an output symbol; and

providing a version of the secondary bit of each symbol decoded from the one or more signals as a primary bit of the output symbol.

48. The apparatus of claim 45, wherein the encoding indicator signal and the one or more signals received from the communications link include pulse amplitude modulation signals having at least 3 levels.

49. The apparatus of claim 45, wherein the first logic state and the second logic state correspond to different boolean logic levels.