Methods and apparatus to reduce signaling power
First Claim
1. A data communications method, comprising:
- determining a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state;
generating transmission symbols from the plurality of input data symbols, wherein the primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and the secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; and
providing the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link.
1 Assignment
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Accused Products
Abstract
System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.
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Citations
49 Claims
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1. A data communications method, comprising:
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determining a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state; generating transmission symbols from the plurality of input data symbols, wherein the primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and the secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; and providing the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An apparatus, comprising:
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means for determining a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state; means for generating transmission symbols from the plurality of input data symbols, wherein the primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and the secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; and means for providing the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. An apparatus, comprising:
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one or more multi-state encoders configured to encode transmission symbols as multi-level transmission symbols for transmission on a pulse amplitude modulated communications link; a processing circuit configured to; determine a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state; generate the transmission symbols from the plurality of input data symbols, wherein the primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and the secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; and provide the transmission symbols to the one or more multi-state encoders. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:
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determine a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state; generate transmission symbols from the plurality of input data symbols, wherein the primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and the secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; and provide the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link. - View Dependent Claims (38, 39, 40)
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41. A method performed by a device, comprising:
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decoding, via a decoding circuit, a multi-level encoding indicator signal received from a communications link to provide a plurality of control signals; selectively inverting, via an inverting circuit, a primary bit of data symbols decoded from one or more signals received from the communications link based on a first of the plurality of control signals; selectively inverting, via the inverting circuit, a secondary bit of the data symbols based on a second of the plurality of control signals; and selectively swapping, via a swapping circuit, the primary bit and the secondary bit based on a third of the plurality of control signals, wherein more power is required to transmit the primary bit or the secondary bit in a first logic state than in a second logic state. - View Dependent Claims (42, 43, 44)
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45. An apparatus, comprising:
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a multi-state decoder configured to decode a multi-level encoding indicator signal received from a communications link and to provide a plurality of control signals extracted from the encoding indicator signal; and a processing circuit configured to; selectively invert a primary bit of data symbols decoded from one or more signals received from the communications link based on a first of the plurality of control signals; selectively invert a secondary bit of the data symbols based on a second of the plurality of control signals; and selectively swap the primary bit and the secondary bit based on a third of the plurality of control signals, wherein more power is required to transmit the primary bit or the secondary bit in a first logic state than in a second logic state. - View Dependent Claims (46, 47, 48, 49)
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Specification