Leakage variation aware power management for multicore processors

• US 9,176,563 B2
• Filed: 05/14/2012
• Issued: 11/03/2015
• Est. Priority Date: 05/14/2012
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Jung, Hwisung
• Primary Examiner(s): Tran, Vincent
• Application Number:
  US13/471,226
• Publication Number:
  US 20130305068A1
• Time in Patent Office: 1,268 Days
• Field of Search: 713/100, 713/300, 713/323, 713/322
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3246 by software initiated power-off
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method are provided to improve power efficiency of processor cores, such as processor cores in a multicore processor. A break-even time of a processor core may be determined that affects which power saving mode a processor core should enter when an expected idle of the processor core is identified. The break-even time of the processor core may be determined during run-time to help determine an applicable power saving mode that improves power efficiency of the processor core.

Claims

1. A method comprising:

measuring, during run time, a first variation indicator of a processor core, wherein the first variation indicator is indicative of leakage power behavior of the processor core;

storing the first variation indicator in a first data structure;

comparing the first variation indicator to a second variation indicator and a third variation indicator stored in a second data structure, the second data structure comprising;

a mapping of the second variation indicator to a first reference break-even time; and

a mapping of the third variation indicator to a second reference break-even time;

responsive to the comparison, determining a power control break-even time accounting for the leakage power behavior of the processor core indicated by the first variation indicator by interpolating between the first and second reference break-even times; and

applying a particular power management mode to the processor core based on the power control break-even time determined for the processor core.

2. The method of claim 1 further comprising:

updating the power control break-even time for applying the particular power management mode to the processor core when the processor core changes performance level.

3. The method of claim 2, wherein updating the break-even time comprises:

updating the power control break-even time for applying the particular power management mode to the processor core when the processor core changes performance level and when no other processor cores are active.

4. The method of claim 1, further comprising:

determining an expected idle time of the processor core.

5. The method of claim 4, wherein applying the particular power management mode comprises:

applying the particular power management mode to the processor core when the expected idle time is less than the power control break-even time of the processor core.

6. The method of claim 5, wherein applying the particular power management mode comprises:

gating a clock associated with the processor core; and

powering off the processor core.

7. The method of claim 1, further comprising determining the second variation indicator via a simulation account for a shutdown action, a wakeup action, or both.

8. A system comprising:

a multicore processor comprising a first processor core and a second processor core;

a memory in communication with the first and second processor cores;

a variation monitor circuit operable to;

measure a first variation indicator of the first processor core, wherein the first variation indicator is indicative of leakage power behavior of the first processor core;

measure a second variation indicator of the second processor core, wherein the second variation indicator is indicative of leakage power behavior of the second processor core; and

store the first and second variation indicators in a first data structure; and

a power manager circuit operable to;

compare the first variation indicator to an array of variation indicators stored in a second data structure, the second data structure comprising a mapping of the array of variation indicators to an array of reference break-even times, the second data structure mapping the array of variation indicators to the multicore processor, the second data structure different from the first data structure;

compare the second variation indicator to the array of variation indicators;

responsive to the comparison of the first variation indicator to the array of variation indicators, assign a first power control break-even time to the first processor core, the first power control break-even time accounting for the leakage power behavior of the first processor core indicated by the first variation indicator;

responsive to the comparison of the second variation indicator to the array of variation indicators, assign a second power control break-even time to the second processor core, the second power control break-even time accounting for the leakage power behavior of the second processor core indicated by the second variation indicator;

identify an expected idle time of the first processor core or the second processor core, or both; and

apply a particular power management mode to the first processor core or the second processor core, or both based on the expected idle time and the first and second power control break-even times.

9. The system of claim 8, wherein the power management circuit is further operable to:

determine when no other processor cores other than the second processor core are active in the multicore processor, and in response;

update the second power control break-even time for applying the particular power management mode when the second processor core changes performance level.

10. The system of claim 8, wherein the power management circuit is operable to apply the particular power management mode by gating a clock associated with the first processor core without powering off the first processor core, gating a clock associated with the second processor core without powering off the second processor core, gating the clock associated with the first processor core and powering off the first processor core, gating the clock associated with the second processor core and powering off the second processor core, or any combination thereof.

11. The system of claim 8, further comprising:

a memory in communication with the first processor core and the second processor core; and

when the expected idle time of the first processor core is greater than the first power control break-even time, the power management circuit is operable to apply the particular power management mode to the first processor core by;

saving content of the memory; and

powering off the memory.

12. The system of claim 8, further comprising:

a memory in communication with the first processor core and the second processor core; and

when the expected idle time of the second processor core is greater than the second power control break-even time, the power management circuit is operable to apply the particular power management mode to the second processor core by;

saving content of the memory; and

powering off the memory.

13. The system of claim 8, wherein the variation monitor circuit comprises a silicon performance monitor.

14. The system of claim 8, wherein the power manager circuit is configured to:

determine when the second processor core transitions from an active state to an inactive state; and

responsive to the determination, update the first power control break-even time for applying the particular power management mode when the first processor core changes performance level.

15. A system comprising:

a processor core;

evaluation circuitry in communication with the processor core, the evaluation circuitry operable to;

obtain a first evaluation of variation of the processor core operating at a first performance level, wherein the first evaluation of variation is indicative of leakage power behavior of the processor core operating at the first performance level; and

store the first evaluation of variation;

compare the first evaluation of variation to an array of variation indicators in a mapping of the array of variation indicators to an array of reference timing thresholds;

responsive to the comparison, interpolate between multiple selected ones of the reference timing thresholds to determine a first power control timing threshold for the first performance level from the first evaluation, the first power control timing threshold accounting for the leakage power behavior of the processor core operating at the first performance level; and

power control circuitry in communication with the processor core, the power control circuitry operable to;

obtain an expected idle time for the processor core; and

determine an applicable power saving mode for the processor core based on the expected idle time and the first power control timing threshold.

16. The system of claim 15, wherein the power control circuitry is operable to determine the applicable power saving mode by determining whether the expected idle time exceeds the first power control timing threshold.

17. The system of claim 15, further comprising a silicon performance monitor in communication with the processor core.

18. The system of claim 15, wherein:

the evaluation circuitry is further operable to;

obtain a second evaluation of variation of the processor core operating at a second performance level, wherein the second evaluation of variation is indicative of the leakage power behavior of the processor core operating at the second performance level; and

determine a second power control timing threshold for the second performance level from the second evaluation, the second power control timing threshold accounting for the leakage power behavior of the processor core operating at the second performance level; and

the applicable power saving mode for the processor core is determined based on;

the expected idle time and the first power control timing threshold when the processor core is operating at the first performance level; and

the expected idle time and the second power control timing threshold when the processor core is operating at the second performance level.

19. The system of claim 15, wherein:

the applicable power saving mode is selected to minimize power consumption of the processor core over the expected idle time.

20. The system of claim 15, wherein:

the applicable power saving mode is selected to minimize power consumption of the processor core over the expected idle time, including power cost for;

stopping the processor core, restarting the processor core, saving a memory state, or any combination thereof.