Controlling operating frequency of a core domain based on operating condition of a non-core domain of a multi-domain processor

• US 9,176,565 B2
• Filed: 03/01/2013
• Issued: 11/03/2015
• Est. Priority Date: 10/27/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishnan, Avinash N., Rotem, Efraim, Rajwan, Doron, Shrall, Jeremy J., Samson, Eric C., Weissmann, Eliezer, Wells, Ryan
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US13/782,578
• Publication Number:
  US 20130179709A1
• Time in Patent Office: 977 Days
• Field of Search: 713300-340, 710306-315
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

Claims

1. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

determining that a first domain of a multi-domain processor is not operating at a frequency requested by the first domain, the first domain comprising one or more graphics engines;

responsive to the determination, sending a request from the first domain to a power controller of the multi-domain processor to reduce a frequency of a second domain of the multi-domain processor, the second domain comprising one or more cores; and

responsive to the request, reducing the frequency of the second domain.

2. The machine-readable medium of claim 1, wherein the method further comprises updating a first field of a configuration register to cause the power controller to reduce a maximum turbo frequency of the second domain.

3. The machine-readable medium of claim 1, wherein reducing the second domain frequency includes causing a maximum turbo frequency of the second domain to be lowered from a fused value to a second turbo value less than the fused value.

4. The machine-readable medium of claim 2, wherein the method further comprises updating a second field of the configuration register to cause the power controller to reduce a guaranteed frequency of the second domain.

5. The machine-readable medium of claim 3, wherein the method further comprises determining whether the second domain is operating at least at a guaranteed frequency.

6. The machine-readable medium of claim 5, wherein the method further comprises causing the guaranteed frequency of the second domain to be lowered from a second fused value to a second guaranteed value less than the second fused value.

7. A processor comprising:

a core domain;

a graphics domain; and

a power controller coupled to the core domain and the graphics domain, wherein the core domain is to operate at a frequency range between a maximum frequency and a guaranteed frequency, the maximum frequency and the guaranteed frequency set at manufacture, wherein the graphics domain is to cause the power controller to dynamically reduce at least one of the maximum frequency and the guaranteed frequency of the core domain.

8. The processor of claim 7, wherein the graphics domain is to update a first field of a configuration register if the graphics domain is operating at a frequency less than a requested frequency.

9. The processor of claim 7, wherein a driver of the graphics domain is to cause the power controller to dynamically reduce the at least one frequency, wherein the driver is to execute on the core domain.

10. The processor of claim 8, wherein the power controller is to limit the maximum frequency based on the updated first field of the configuration register.

11. The processor of claim 8, wherein the graphics domain is to thereafter update a second field of the configuration register.

12. The processor of claim 11, wherein the power controller is to limit the guaranteed frequency based on the updated second field of the configuration register.

13. The processor of claim 8, wherein the configuration register is located in the power controller, and is accessible to the graphics domain.

14. The processor of claim 8, wherein a driver of the graphics domain is to access the configuration register, wherein the driver is to execute on the core domain.

15. A system comprising:

a multi-domain processor including a core domain, a graphics domain, and a power controller, the core domain to operate at a frequency range between a maximum frequency and a guaranteed frequency, the maximum frequency and the guaranteed frequency set at manufacture, wherein the power controller includes a configuration register accessible to the graphics domain, the configuration register to store at least one value to be written by a driver of the graphics domain to enable a dynamic reduction in a frequency range at which the core domain can operate; and

a dynamic random access memory (DRAM) coupled to the multi-domain processor.

16. The system of claim 15, wherein the driver of the graphics domain is allowed to write to the configuration register when a first graphics domain workload is executing, and is prevented from writing to the configuration register when a second graphics domain workload is executing.

17. The system of claim 15, wherein the power controller includes a second configuration register accessible to the core domain, the second configuration register to store at least one value to be written by the core domain to enable a dynamic reduction in a frequency range at which the graphics domain can operate.

18. The system of claim 15, wherein the graphics domain is to operate at a higher frequency after the dynamic reduction in the core domain frequency range.

19. The system of claim 15, wherein the power controller is to first reduce the maximum frequency of the core domain, and to thereafter reduce the guaranteed frequency of the core domain only if the graphics domain is not operating at a requested frequency after the maximum frequency reduction.

20. The system of claim 15, wherein responsive to update to the configuration register, the power controller is to cause the core domain to operate at a frequency less than the guaranteed frequency set at manufacture, wherein the frequency less than the guaranteed frequency violates an operating system guaranteed frequency.