Priority scheduling of threads for applications sharing peripheral devices

• US 9,176,771 B2
• Filed: 02/28/2013
• Issued: 11/03/2015
• Est. Priority Date: 08/11/2009
• Status: Active Grant

• Current Assignee: Clarion Co., Ltd. (Faurecia SA)
• Original Assignee: Clarion Co., Ltd. (Faurecia SA)
• Inventors: Nagai, Yasushi
• Primary Examiner(s): An, Meng
• Assistant Examiner(s): Lee, James J
• Application Number:
  US13/781,578
• Publication Number:
  US 20130174173A1
• Time in Patent Office: 978 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A data processing method has a device control thread for each peripheral device capable of an independent operation, a CPU processing thread for each data processing that is performed by a CPU, a control thread equipped with a processing part for constructing an application. The control thread checks an output from the thread related with each processing part, performs with a higher priority from the processing part in which output data of the preprocessing part as a configuration of the application exists and that is near termination, and instructs execution of the each device control thread and the CPU processing thread, and data input/output. Each of device control thread and CPU processing thread processes the data according to the instructions, and sends a processing result and a notification to the control thread.

Claims

1. A data processor comprising:

a CPU;

a plurality of peripheral devices; and

a memory comprising;

a plurality of device control threads for controlling operation of respective peripheral devices;

a control thread including a plurality of processing parts associated with respective device control threads;

a table storing configurations of a plurality of applications including application priority of respective applications, wherein each application includes an operation sequence of processing parts that constitute an application and a dependence relationship between the processing parts of the application, wherein the processing parts are prioritized such that processing part near end of the operation sequence is performed with higher priority than processing part near beginning of the operation sequence;

a program, when executed by the CPU, executes the control thread to perform the method of;

executing two or more of the applications sharing at least one peripheral device in parallel,

wherein when an overlap between operation timings of respective processing parts of the two or more of the applications corresponding to a same peripheral device occurs, processing part with higher priority is executed before respective processing parts of other applications, wherein

if priorities associated with the respective processing parts are the same, application priority of application associated with processing part that last executed is lowered such that processing part of the other application with higher priority is executed, and

if each of the respective processing parts has no dependence relationship based on the configuration stored in the table, no priority is given to the respective processing parts such that the respective processing parts are executed in alternate manner.

2. The data processor according to claim 1, wherein:

the plurality of the applications are defined by the table, and

the control thread for executing peripheral device control instructs to execute a sequences of processing parts defining a target application, according to the application priority provided to each of the applications, and to lower the application priority of the target application versus other applications, when control of the target application is returned to the control thread for executing peripheral device control.

3. The data processor according to claim 2, wherein among the applications the application priorities of which are equal, the application priority of an application corresponding to the processing part instructed last to be executed is lowered.

4. The data processor according to claim 1,

wherein a plurality of threads include the device control threads for controlling peripheral devices and CPU processing threads each corresponding to a predetermined data processing to be executed by the CPU,

in response to an instruction of execution, each of the device control threads controls the corresponding peripheral device according to the instruction,

in response to a completion notification from the corresponding peripheral device, each of the device control threads sends to the control thread a processing result of the corresponding peripheral device and the completion notification, and

in response to another instruction of execution, each of the CPU processing threads executes the predetermined data processing according to the another instruction, and sends to the control thread a processing result of the predetermined data processing and a notification.