Bit error reduction through varied data positioning

• US 9,176,810 B2
• Filed: 05/29/2012
• Issued: 11/03/2015
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Peterson, Jim, Strasser, John, Hyun, Jea
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US13/482,892
• Publication Number:
  US 20120304039A1
• Time in Patent Office: 1,253 Days
• Field of Search: 714/763, 714/761, 714766-767, 714773-774, 714/787, 714/805, 714/739, 714/746, 714/6.1, 714/6.2, 714/6.24, 714/48, 714/52, 714/54, 714/704, 711/100, 711/104, 711/114, 711/127, 711/150, 711/103, 365/189.01, 365/189.04
• US Class Current: 1/1
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence

Abstract

Devices, apparatuses, systems, and methods are disclosed for bit error reduction through varied data positioning. A write request module is configured to receive data for storage in an array of solid-state storage elements. The solid-state storage elements are accessible in parallel. A write module is configured to store the data in parallel to the array of solid-state storage elements with varied data positions for the data relative to different solid-state storage elements of the array. A read module is configured to read the data in parallel from the array of solid-state storage elements.

Claims

1. A method, comprising:

receiving data for storage in an array of solid-state storage elements, the solid-state storage elements comprising data positions having respective error rates, wherein one or more of the data positions have an error rate that differs from an average error rate of the array;

storing the received data at a plurality of data positions within the array, wherein each of the plurality of data positions corresponds to a respective solid-state storage element, wherein storing the received data further comprises varying data positions of the received data within the respective solid-state storage elements in accordance with the error rates corresponding to the data positions; and

reading data from the varied data positions within the respective solid-state storage elements in the array of solid-state storage elements.

2. The method of claim 1, further comprising determining a different address for each of the different data positions based on known reliability characteristics of the different data positions within the array of solid-state storage elements.

3. The method of claim 2, further comprising sending the different addresses in parallel to the solid-state storage elements of the array to store the data and to read the data.

4. The method of claim 2, wherein the different address for each of the different data positions comprises adding a predetermined offset to addresses to define each of the different data positions according to an order of the solid-state storage elements of the array.

5. The method of claim 1, wherein the data is stored as a logical page spanning the solid-state storage elements in the array.

6. The method of claim 1, wherein the different data positions comprise one or more of solid-state storage dies having different relative positions within the solid-state storage elements of the array, physical pages disposed in different positions relative to the solid-state storage elements of the array, one or more upper pages and one or more lower pages of the solid-state storage elements of the array, physical erase blocks disposed in different physical positions relative to the solid-state storage elements of the array, and one or more odd physical pages and one or more even physical pages of the array of solid-state storage elements.

7. The method of claim 1, wherein the data comprises a logical page of data and the different data positions comprise physical pages disposed in different positions relative to the solid-state storage elements of the array.

8. The method of claim 7, further comprising inverting an address bit for solid-state storage elements of the array to alternate the different data positions between the one or more upper pages and the one or more lower pages of the multi-level memory cells.

9. The method of claim 7, further comprising restructuring logical pages of the array of solid-state storage elements from physical pages disposed in similar positions relative to the solid-state storage elements of the array to the physical pages disposed in different positions in response to a number of program/erase cycles satisfying a threshold.

10. The method of claim 7, further comprising buffering the data with other data such that the data and the other data is stored to the physical pages in an order that satisfies a write order for the solid-state storage elements of the array.

11. An apparatus, comprising:

a data position module configured to arrange a data segment for storage within a logical page, the logical page comprising physical pages on each of a plurality of solid-state storage elements of an array, the physical pages having respective reliability characteristics that vary within the respective solid-state storage elements, such that reliability characteristics of certain physical pages differ from average reliability characteristics of the physical pages of the array, wherein the data position module is configured to select varied data positions for the physical pages of the logical page in accordance with the varied reliability characteristics of the physical pages within the respective solid-state storage elements;

a write module configured to store the data segment the logical page arranged by the data position module ; and

a read module configured to read the stored data segment from the logical page arranged by the data position module.

12. The apparatus of claim 11, further comprising an address module configured to determine a different address for each of the physical pages at the varied data positions within the respective solid-state storage elements of the array.

13. The apparatus of claim 11, wherein enable lines are electrically coupled to the different solid-state storage elements of the array in different relative locations of the different solid-state storage elements such that the array of solid-state storage elements is configured to receive the data segment in parallel at the varied data positions.

14. The apparatus of claim 11, wherein the varied data positions comprise solid-state storage dies having different relative positions within the different solid-state storage elements of the array.

15. The apparatus of claim 11, wherein the data segment comprises an error correcting code codeword.

16. The apparatus of claim 11, wherein the logical page comprises one or more upper pages and one or more lower pages of respective multi-level memory cells.

17. The apparatus of claim 11, wherein the logical page spans more than one logical erase block of the array of solid-state storage elements.

18. The apparatus of claim 11, wherein the logical page comprises physical pages within respective physical erase blocks at different physical positions relative to the different solid-state storage elements of the array.

19. The apparatus of claim 11, wherein the varied data positions comprise one or more odd physical pages and one or more even physical pages of the array of solid-state storage elements.

20. The apparatus of claim 11, wherein the varied data positions comprise a combination of two or more of solid-state storage dies having different relative positions within the different solid-state storage elements of the array, one or more upper pages and one or more lower pages of the array of solid-state storage elements, and physical pages disposed in different positions relative to the different solid-state storage elements of the array.

21. The apparatus of claim 11, wherein the varied data positions are selected to average an error rate across the plurality of physical pages of the logical page.

22. A system comprising:

a solid-state storage device comprising a plurality of solid-state storage elements, each solid-state storage element comprising a plurality of physical storage locations at respective physical addresses, each physical storage location having a respective error rate, wherein the error rates of the physical storage locations differ in accordance with the physical addresses of the physical storage locations; and

a storage controller, comprising,

a write module configured to store an error correcting code chunk in parallel across the plurality of solid-state storage elements, wherein data of the error correcting code chunk are stored in physical storage locations within a plurality of different solid-state storage elements and at varied physical address offsets within the respective solid-state storage elements, wherein the physical address offsets are varied in accordance with the error rates of the physical storage locations at different physical addresses within the respective solid-state storage elements ; and

a read module configured to read the error correcting code chunk in parallel from the array of solid-state storage elements.

23. The system of claim 22, further comprising a host computing system in communication with the solid-state storage device over one or more communications buses.

24. A non-transitory computer program product comprising a computer readable storage medium storing computer usable program code executable to perform operations, the operations of the computer program product comprising:

determining a plurality of different addresses for a virtual page, each address of the virtual page corresponding to a physical data position within a respective one of a plurality of solid-state storage elements in a storage array, wherein error rates of the physical data positions vary in accordance with the respective addresses of the physical data positions within the array, wherein determining the plurality of different addresses for the virtual page comprises selecting addresses at different offsets within the respective solid-state storage elements such that the virtual page comprises physical data positions corresponding to different error rates within the array;

sending the plurality of different addresses in parallel to the solid-state storage elements of the storage array; and

storing data in parallel to the physical data positions within the respective solid-state storage elements at the plurality of different addresses determined for the virtual page.

25. An apparatus, comprising:

means for receiving data for storage in an array of solid-state storage elements, the solid-state storage elements accessible in parallel, the solid-state storage elements comprising storage locations at respective data positions within the array, wherein error rates of the storage locations vary based on data position of the storage locations within the array;

means for storing the received data to a plurality of storage locations within the array in parallel, each of the plurality of storage locations corresponding to a respective one of the solid-state storage elements such that the data is stored in storage locations at different data positions relative to the solid-state storage elements of the array, the different data positions selected to average an error rate of the plurality of storage locations based on the varied error rates of the data positions of the plurality of storage locations within the array; and

means for reading data in parallel from the array of solid-state storage elements.