Translation layer in a solid state storage device

• US 9,176,868 B2
• Filed: 02/05/2015
• Issued: 11/03/2015
• Est. Priority Date: 10/13/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy
• Primary Examiner(s): Tseng, Cheng-Yuan
• Assistant Examiner(s): GOLDSCHMIDT, CRAIG S
• Application Number:
  US14/614,623
• Publication Number:
  US 20150149712A1
• Time in Patent Office: 271 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.

Claims

1. A solid state device comprising:

a controller;

wherein the controller is configured to perform a first division operation that divides a received logical block address that indicates a physical memory block in a memory device of a plurality of memory devices in the solid state device by a number of logical block addresses per page of the physical memory block to obtain a result of the first division operation;

wherein the controller is configured to perform a second division operation that divides the obtained result of the first division operation by a number of memory devices in the plurality of memory devices;

wherein the controller is configured to determine a location of the memory device of the plurality of memory devices within the solid state device from a location in a memory device table, wherein the location in the memory device table is identified by a remainder of the second division operation;

wherein the controller is configured to generate a data block look-up table comprising the received logical block address, wherein the received logical block address is associated with a data block look-up table entry that comprises a first portion configured to indicate a highest programmed page of the physical memory block and a second portion that is different from the first portion and that is configured to indicate that the physical memory block is ordered when the physical memory block is ordered and to indicate that the physical memory block is not ordered when the physical memory block is not ordered.

2. The solid state device of claim 1, wherein when the physical memory block is ordered, the received logical block address comprises a number of a page within the physical memory block and a position in that page.

3. The solid state device of claim 1, wherein data block look-up table entry comprises a third portion that points to the physical block.

4. The solid state device of claim 1, wherein the received logical block address is a sector number of a sector request.

5. The solid state device of claim 4, wherein sector request comprises a read command or a write command.

6. The solid state device of claim 1, wherein the logical address corresponds to a portion of a page of the physical memory block.

7. The solid state device of claim 1, wherein the controller comprises a Flash Translation Layer.

8. The solid state device of claim 1, wherein the controller is configured to locate the physical block in the data block look-up table in response to the logical block address.

10. The solid state device of claim 1, wherein the controller is configured to store the parallel unit look-up table in RAM of the solid state device.

11. The solid state device of claim 1, wherein the controller is configured to store the parallel unit look-up table in a memory block of a parallel unit determined to exist within the solid state device.

12. The solid state device of claim 11, wherein the controller being configured to store the parallel unit look-up table in the memory block of the parallel unit determined to exist within the solid state device comprises the controller being configured to store the parallel unit look-up table in a memory block that is determined to be free of errors.

9. A solid state device, comprising:

a controller;

wherein the controller is configured to determine the existence of parallel units within the solid state device;

wherein the controller is configured to generate a parallel unit look-up table that includes locations within the solid state device of the parallel units determined to exist within the solid state device;

wherein the controller is configured to determine a location within the solid state device of a target parallel unit that is determined to exist within the solid state device by determining an index for the target parallel unit and finding the location within the solid state device of the target parallel unit from a location in the parallel unit look-up table identified by the index for the target parallel unit, wherein the index for the target parallel unit is determined by dividing a logical block address indicating a memory block in the target parallel unit by a number of logical block addresses per page of the memory block to produce a first result and by performing a modulo operation dividing the first result by a number of memory devices in the parallel look up table to produce a second result, wherein the second result is the index for the target parallel unit;

wherein the controller is configured to generate a data block look-up table comprising addresses the logical block address, indicating the memory block in the target parallel unit, the logical block address associated with a data block look-up table entry, comprising a first portion configured to indicate a highest programmed page of the memory block and a second portion that is different from the first portion and that is configured to indicate that the memory block is ordered when the memory block is ordered and to indicate that the memory block is not ordered when the memory block is not ordered.

13. A method of operating solid state device, the method comprising:

determining a location of a memory device within the solid state device from location characteristics for the memory device that are at a location in a memory device table, wherein the location in the memory device table is identified by an index for the memory device; and

generating a data block look-up table comprising a logical block address in the memory device, wherein the logical block address in the memory device is associated with a data block look-up table entry that comprises a first portion configured to indicate a highest programmed page of a physical memory block indicated by the logical block address and a second portion that is different from the first portion and that is configured to indicate that the physical memory block is ordered when the physical memory block is ordered and to indicate that the physical memory block is not ordered when the physical memory block is not ordered;

wherein the index for the memory device is calculated by dividing the logical block address by a number of logical block addresses per page of the physical memory block to produce a first result and by performing a modulo operation dividing the first result by a number of memory devices in the memory device table to produce a second result, wherein the second result is the index.

14. The method of claim 13, further comprising generating the memory device table.

15. The method of claim 13, further comprising receiving the logical block address from a host.